Delay Locked Loop Pulse Selection for Faster Tracking
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Solution Overview
Problem
Conventional delay locked loops require several feedback operations, leading to increased tracking time due to accumulated delay in the delay model circuit, resulting in longer tracking times.
Innovation Solution
A delay locked loop design that includes a pulse generation circuit, pulse retainer circuit, pulse selection circuit, and additional phase comparator circuits to generate and control pulse signals, allowing for precise adjustment of the variable delay line circuit's delay, thereby shortening the tracking time by using pulse signals and feedback signals to align edges and control the delay amount.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If several feedback operations are performed to complete the tracking operation, then the delay amount is determined, but the tracking time increases due to accumulated delay
Solution Approach 1:
The pulse generation circuit generates a pulse signal in advance during the tracking operation, which is then used by the pulse selection circuit to provide a corrected input signal to the variable delay line circuit. This preliminary action allows the system to determine the delay amount faster by using the generated pulse signal instead of waiting for multiple feedback operations to complete, thereby reducing tracking time while maintaining delay determination accuracy
Solution Approach 2:
The pulse generation circuit and pulse selection circuit act as intermediaries between the phase comparator circuit and the variable delay line circuit. The pulse generation circuit generates a pulse signal based on the phase difference detection, and the pulse selection circuit selects between the original input signal and the generated pulse signal to provide to the variable delay line circuit. This intermediary mechanism enables faster tracking by providing a corrected signal path that reduces the number of feedback operations needed
Data Source
AI summary
A delay locked loop includes a variable delay line circuit configured to delay a pulse selection circuit output to generate an output signal, a delay model circuit to delay the output signal to generate a first feedback signal, a first phase comparator circuit to control the variable delay line circuit according to the input signal and the first feedback signal, a pulse generation circuit to generate a pulse signal according to the input signal and the first feedback signal, a pulse retainer circuit to delay the output signal to generate a second feedback signal, a pulse selection circuit to select the pulse signal generated by the pulse generation circuit or the second feedback signal as the pulse selection circuit output during the tracking operation, and a second phase comparator circuit to control the variable delay line circuit according to the pulse selection circuit output and the output signal.