Delay-Locked Loop Circuit Using Coarse-Fine Delay Cells for Low Power
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Solution Overview
Problem
Conventional DLL circuits face challenges in reducing power consumption while maintaining high-speed operation, as they either increase signal loading and jitter or are heavily influenced by PVT variables, limiting their performance in high-speed semiconductor devices like DRAMs.
Innovation Solution
A DLL circuit design that employs a combination of differential amplifier-based delay cells for fine locking and inverter-based delay cells for coarse locking, with a replica delay path for compensation, to minimize power consumption and robustly withstand PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional inverter-based delay cells are used for high-speed operation, then speed is improved, but power consumption increases and the circuit becomes heavily influenced by PVT variables
Solution Approach 1:
The delay line is segmented into multiple delay cells, each contributing a portion of the total delay. This allows the circuit to achieve the required delay function with fewer active cells, reducing overall power consumption while maintaining high-speed operation capability.
Solution Approach 2:
Different delay cells are designed with different characteristics (e.g., varying delay amounts, different circuit configurations) to optimize performance at different stages of the delay line. This local differentiation allows the circuit to achieve high-speed operation where needed while minimizing power consumption in other stages.
2Measurement precision
If more delay cells are added to increase delay range, then delay precision is improved, but device complexity increases
Solution Approach 1:
The delay line incorporates dynamically controllable delay cells that can adjust their delay amount based on control signals. This dynamic capability allows the circuit to achieve fine delay precision without requiring a large number of fixed delay cells, thereby reducing circuit complexity.
Solution Approach 2:
The delay characteristics of the delay cells are made可调 (adjustable) through parameter changes such as controlling transistor gate voltages or switching between different circuit configurations. This allows precise delay control without increasing the number of physical delay cells, simplifying the overall circuit structure.
Data Source
AI summary
A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.