Delay Locked Loop Replica Fine Delay for Faster Clock Locking
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Solution Overview
Problem
Existing delay locked loops experience increased locking time and clock signal skew due to the replication of internal circuits, which can lead to longer synchronization times and increased jitter in electronic devices.
Innovation Solution
A delay locked loop apparatus comprising a coarse delay circuit, a fine delay circuit, and a third delay circuit, along with a phase detector and controller, that adjust delay amounts to synchronize clock signals efficiently, including a replica fine delay circuit to reduce loop delay and clock signal skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If replica circuits are implemented by replicating internal circuits for synchronization, then synchronization accuracy is improved, but locking time increases
Solution Approach 1:
The delay circuit is divided into multiple delay units (first delay unit, second delay unit, third delay unit) that can be independently controlled. This segmentation allows the system to achieve fine-grained delay adjustment without requiring a large number of replica circuits, thereby reducing locking time while maintaining synchronization accuracy.
Solution Approach 2:
The delay amounts of the delay units are dynamically adjustable through control signals generated by the controller based on phase detector feedback. This dynamic adjustment capability enables the system to quickly converge to the correct synchronization point, reducing locking time while maintaining high synchronization accuracy.
2Measurement precision
If the number of replica circuits is increased to reduce clock signal skew, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
Instead of increasing the number of replica circuits, the invention changes the delay parameters (delay amounts) of existing delay units to achieve clock signal skew compensation. This parameter-based approach reduces device complexity while maintaining the ability to accurately compensate for skew.
Solution Approach 2:
The invention uses a simplified replica structure with adjustable delay units rather than full replica circuits. This partial copying approach maintains the essential function of skew compensation while significantly reducing the complexity associated with implementing complete replica circuits.
3Measurement precision
If delay amounts are adjusted to synchronize clock signals, then synchronization accuracy is improved, but jitter increases
Solution Approach 1:
The phase detector continuously monitors the phase difference between clock signals and provides feedback to the controller, which adjusts the delay amounts accordingly. This closed-loop feedback mechanism enables accurate phase synchronization while maintaining signal stability by making incremental adjustments rather than large, destabilizing changes.
Solution Approach 2:
The system dynamically adjusts delay amounts in response to phase error signals, allowing it to quickly acquire synchronization and then maintain stable operation. The dynamic control enables the system to adapt to changing conditions while preserving signal stability through controlled, feedback-driven adjustments.
Data Source
AI summary
In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.