Delay Lock Loop Delay Line With Switchable Arrays for Low Power
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Solution Overview
Problem
As integrated circuits become faster and more integrated, they experience increased power consumption, necessitating a reduction in clock skews and jitters while maintaining low power consumption.
Innovation Solution
A delay lock loop system comprising a decoder, first and second delay arrays, a multiplexer, and a phase detector, which uses control signals to manage power consumption by selectively enabling and disabling delay arrays to optimize clock signal delays and phase alignment, thereby reducing unnecessary power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the speed of integrated circuits is increased to improve performance, then productivity is improved, but power consumption increases
Solution Approach 1:
The delay line is divided into multiple delay units (first delay unit, second delay unit, third delay unit) that can be independently controlled. Each delay unit contains delay elements that can be selectively enabled or disabled through control signals, allowing the circuit to segment its operation and activate only the necessary portions for the current operating conditions.
Solution Approach 2:
The delay line incorporates dynamic control mechanisms where control signals adjust the activation state of different delay units based on operating requirements. The first control signal and second control signal dynamically enable or disable specific delay elements, allowing the circuit to adapt its power consumption and delay characteristics in real-time.
2Reliability
If delay lock loop is used for clock calibration to reduce clock skews and jitters, then reliability is improved, but power consumption increases
Solution Approach 1:
The delay lock loop's delay line is segmented into multiple independently controllable delay units. This segmentation allows the system to activate only the minimum necessary delay elements required for achieving phase lock, rather than continuously powering all delay elements, thus maintaining calibration reliability while reducing power consumption.
Solution Approach 2:
The system changes the operational parameters of the delay line by adjusting control signals that modify the activation state of delay units. By dynamically changing these parameters based on phase detection results, the system maintains reliable clock calibration while optimizing power consumption according to actual operating conditions.
Data Source
AI summary
A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay array clock signal according to the delay control signal. The second delay array receives a power control signal, the first delay array clock signal and the delay control signal. The second delay array is turned on or off according to the power control signal. If the second delay array is turned on, the second delay array delays the first delay array clock signal to output a second delay array clock signal according to the delay control signal. The multiplexer receives a selecting control signal, the first and second delay array clock signals, and outputs the first delay array clock signal or the second delay array clock according to the selecting control signal.