Delay-Matched Buffer Circuit Across Multiple Supply Voltages
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Solution Overview
Problem
In multiple supply voltage applications, achieving good delay matching between input and matching buffers in electronic circuits is challenging due to differences in supply voltages and process parameters, leading to mismatches and increased chip gate count or reduced speed.
Innovation Solution
A buffer circuit architecture that includes an input stage and an output stage with low-threshold voltage MOS devices, along with a delay control circuit using high-threshold voltage MOS devices to control delay as a function of supply voltage and temperature, eliminating the need for additional delay matching circuitry and timing budget increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If voltage level translation circuitry is used to translate between core voltage and IO voltage, then delay matching between input buffer and matching buffer is achieved, but additional delay is introduced by the translation itself causing mismatch
Solution Approach 1:
The patent extracts the delay control function from the voltage level translation circuitry by using separate high-voltage transistors dedicated solely to delay adjustment. This isolation allows delay control without introducing translation delay, resolving the contradiction between achieving delay matching and avoiding additional delay.
Solution Approach 2:
The patent introduces high-voltage transistors as intermediary elements between the low-voltage buffer circuitry and the delay control mechanism. These intermediary transistors enable delay adjustment through their variable resistance characteristics without requiring voltage level translation, thus achieving delay matching without additional translation delay.
2Manufacturing precision
If delay matching circuitry is added to compensate for voltage differences, then delay matching is improved, but chip gate count per unit area increases
Solution Approach 1:
The high-voltage transistors serve multiple functions: they act as delay control elements, voltage level adapters, and process variation compensators simultaneously. This multi-functionality achieves delay matching without requiring separate dedicated delay matching circuitry, thereby avoiding increased chip gate count.
Solution Approach 2:
The patent changes the operating parameters of the buffer circuit by introducing high-voltage transistors that can be controlled through process parameters (transistor sizing, threshold voltage selection) to achieve delay matching. This parameter-based approach replaces the need for additional matching circuitry, maintaining compact chip area.
3Manufacturing precision
If delay matching circuitry is added to compensate for voltage differences, then delay matching is improved, but maximum operating speed decreases
Solution Approach 1:
The patent introduces dynamic delay control through high-voltage transistors whose resistance can be adjusted to optimize performance. This dynamic adjustment capability allows the circuit to maintain delay matching across process variations while preserving maximum operating speed, as the transistors can be optimized for speed-critical paths.
Solution Approach 2:
By changing transistor parameters (threshold voltage, dimensions) in the delay control path, the patent enables fine-tuning of delay characteristics without degrading the maximum operating speed of the buffer circuit. The high-voltage transistors are designed with parameters that allow fast switching while providing sufficient delay control range.
Data Source
AI summary
A buffer circuit includes an input stage including at least one MOS device having a first threshold voltage associated therewith, the input stage being adapted to receive an input signal referenced to a first voltage supply. The buffer circuit further includes an output stage including at least one MOS transistor having the first threshold voltage associated therewith, an input of the output stage being connected to an output of the input stage, the output stage being operative to generate an output signal which is indicative of a logic state of the input signal. The buffer circuit includes a delay control circuit adapted for connection between at least one of the first voltage supply and a voltage return of the buffer circuit, and at least one of the input stage and the output stage. The delay control circuit includes at least one MOS device having a second threshold voltage associated therewith. The MOS device in the delay control circuit being adapted to receive, as a control signal, a second voltage supply, a delay of the buffer circuit being at least partially controlled as a function of a process parameter, the second voltage supply and/or a temperature of the MOS device in the delay control circuit.