Delay Memory Architecture for Multi-Signal DSP Processing
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Solution Overview
Problem
Existing digital signal processing (DSP) circuits face challenges in efficiently processing multiple signals, as traditional solutions either require duplicating hardware or significantly slow down processing when buffering and serially processing signals in a single instantiation.
Innovation Solution
A DSP apparatus comprising a DSP module and a delay memory with multiple memory cells, allowing for the storage and processing of digital signal samples from multiple signals in a single instantiation, enabling timely processing of multiple signals without hardware duplication or significant slowdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DSP circuits are duplicated to process multiple signals simultaneously, then processing speed is maintained, but hardware complexity and resource requirements increase
Solution Approach 1:
The patent combines multiple signal processing functions into a single DSP circuit by integrating a delay memory with multiple memory cells that can store samples from multiple signals simultaneously. The circuit processes multiple signals through time-division multiplexing, where the delay memory manages samples from different signals and the single DSP circuit processes them sequentially at different time slots, thereby maintaining processing speed while reducing hardware complexity
Solution Approach 2:
The patent implements dynamic signal routing and processing within the single DSP circuit. The delay memory dynamically allocates storage locations for different signals based on their arrival, and the control logic dynamically switches between processing different signals at different time intervals. This dynamic approach allows one DSP circuit to effectively handle multiple signals without requiring static hardware duplication
2Device complexity
If signals are buffered and processed serially in a single DSP circuit, then hardware requirements are reduced, but processing speed decreases
Solution Approach 1:
The patent applies preliminary action by pre-storing signal samples in the delay memory before DSP processing occurs. Multiple signals are buffered in advance in separate memory cells, allowing the single DSP circuit to process them sequentially without waiting for new samples to arrive during processing. This pre-buffering mechanism maintains processing speed by ensuring data is ready when the DSP circuit is available
Solution Approach 2:
The patent implements periodic action through time-division multiplexed processing of different signals. The single DSP circuit processes signals from different sources in periodic time slots, alternating between different signal streams in a regular pattern. This periodic processing approach allows efficient utilization of the single DSP circuit while maintaining overall processing speed across multiple signals
3Adaptability or versatility
If a delay chain of multiple delays is used to process a single signal, then DSP algorithms can operate on sequential samples, but the solution cannot efficiently handle multiple signals
Solution Approach 1:
The patent achieves universality by designing a delay memory structure where each memory cell can serve multiple signal sources. The same memory cells that provide delayed samples for a single signal's DSP algorithm also accommodate samples from multiple different signals by switching the input source. This multi-functional design allows the circuit to maintain full DSP algorithm capability while adding multi-signal processing versatility
Solution Approach 2:
The patent transitions from a one-dimensional delay chain handling a single signal to a multi-dimensional structure where the delay memory has both time-delay dimension and signal-source dimension. By adding the signal-source dimension through multiple input channels and switchable routing, the system can process multiple signals while maintaining the time-delay functionality needed for DSP algorithms
Data Source
AI summary
A digital signal processing (DSP) apparatus can be used to process a serial stream of digital signal samples of a plurality of “n” number of different signals. The DSP apparatus can include a DSP module configured to perform a DSP algorithm on digital signal samples of the signals. The DSP apparatus can have a delay memory with an “n” number of memory cells that each corresponding to one of the signals. The delay memory can also have a digital signal sample input connected to said initial input of said DSP module, a signal-number-in input, a signal-number-out input, and a digital signal sample output connected to said delay input of said DSP module. The delay memory can be configured to store a digital signal sample at the digital signal sample input in a memory cells identified by a signal identifier at said signal-number-in input. The delay memory can also be configured to output at the digital signal sample output a digital signal sample stored in a memory cells identified by a signal identifier at the signal-number-out input.