Delay-Based Sensing Circuit for Charge Trap Transistors
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Solution Overview
Problem
Conventional sensing circuits for charge trap transistors are slow in sensing data due to their reliance on differential current sense amplifiers, which limits their ability to quickly determine the threshold voltage difference between true and complement transistors in twin cell circuits.
Innovation Solution
A delay-based sensing circuit that uses two identical paths to race signals to a data port and a clock port of a Flip-Flop circuit, with a wordline voltage set at a statistical average of the twin cell threshold voltage plus overdrive voltage, allowing for rapid determination of data stored in a twin cell transistor pair by comparing delays through first and second delay path circuits connected to the true and complement transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a differential current sense amplifier is used to sense the current threshold voltage, then the sensing operation can be performed, but the sensing speed is slow (around 10 nanoseconds)
Solution Approach 1:
The patent replaces the conventional differential current sense amplifier with a delay-based sensing mechanism that utilizes the threshold voltage difference to create different delay paths. Instead of measuring current directly, the system measures the time delay difference between two signal paths that pass through transistors with different threshold voltages, achieving faster sensing speed (around 1 nanosecond).
Solution Approach 2:
The patent changes the sensing parameter from current measurement to time delay measurement. By setting the wordline voltage to a statistical average of the twin cell threshold voltage plus overdrive voltage, the system creates a race condition where the signal path through the transistor with lower threshold voltage arrives first, enabling fast sensing based on time difference rather than current magnitude.
2Productivity
If conventional sensing circuits are used, then data sensing can be achieved, but the sensing operation is slow which limits data processing efficiency
Solution Approach 1:
The patent performs preliminary setup by programming one of the twin cell transistors before the sensing operation. This creates a predetermined threshold voltage difference between the two transistors, which is then exploited during the race condition to determine the stored data. The preliminary programming action ensures that the threshold voltage difference exists before sensing begins, enabling rapid detection.
Solution Approach 2:
The system substitutes the slow differential current measurement with a fast delay-based comparison mechanism. By racing two signals through different transistor paths and comparing their arrival times at a logic circuit, the system achieves much faster data sensing (around 1 nanosecond vs. 10 nanoseconds), directly improving data processing efficiency.
3Speed
If the wordline voltage is set at statistical average of twin cell threshold voltage plus overdrive voltage, then the race condition can be created for fast sensing, but the circuit complexity increases
Solution Approach 1:
The logic circuit in the patent serves multiple functions: it receives the delayed signals from both paths, compares their arrival times, and outputs the sensed data. This multi-functional approach consolidates the sensing and comparison operations into a single circuit block, reducing overall device complexity while maintaining fast sensing capability.
Solution Approach 2:
The patent changes the operating parameter of the transistors by setting the wordline voltage to a specific value (statistical average of threshold voltages plus overdrive voltage). This parameter change enables the race condition to occur naturally, allowing the circuit to sense data based on timing differences rather than requiring complex comparison circuitry, thus balancing speed improvement with complexity management.
Data Source
AI summary
The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.