Delay Signal Circuit Layout for Low-Deviation CAN Timing
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Solution Overview
Problem
Existing CAN communication systems in vehicles face challenges in minimizing delay time deviations among multiple delay signals, which can lead to noise and inefficiencies in communication due to the need for long and complicated wiring.
Innovation Solution
A delay signal generation circuit is configured to generate a plurality of delay signals with minimal time deviations by using a combination of delay circuits and variable resistance circuits, allowing for flexible resistance value control based on transmission data, and optimizing the arrangement of delay circuits to reduce wiring length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple delay circuits are used to generate multiple delay signals, then the delay signals can be generated with different delay times, but the delay time deviations among the delay signals increase due to long and complicated wiring
Solution Approach 1:
The patent combines multiple delay circuits into a single integrated delay circuit that generates multiple delay signals simultaneously. This merging approach eliminates the need for separate wiring paths for each delay circuit, thereby reducing the delay time deviations caused by long and complicated wiring while maintaining the ability to generate multiple delay signals with different delay times.
Solution Approach 2:
The patent introduces a variable resistance circuit connected in parallel with the delay circuit, adding a new dimension of control through resistance adjustment. This allows dynamic modification of the delay characteristics without adding more physical delay circuits or extending wiring, thereby reducing delay time deviations while maintaining versatility in generating multiple delay signals.
2Adaptability or versatility
If the wiring between delay circuits is extended to accommodate multiple ECUs, then more ECUs can be connected to the CAN bus, but the delay time deviations among delay signals increase
Solution Approach 1:
The patent merges multiple delay circuit functions into a single integrated circuit located at one ECU. This consolidation eliminates the need for extended wiring between multiple delay circuits across different ECUs, thereby reducing delay time deviations and improving communication reliability while still supporting multiple ECUs on the CAN bus through the single integrated delay signal generation.
Solution Approach 2:
The patent introduces a variable resistance circuit as an intermediary element that mediates the delay signal generation process. By adjusting the resistance value, the system can dynamically control the delay characteristics to compensate for wiring variations, thereby maintaining communication reliability even when multiple ECUs are connected through extended wiring.
3Ease of manufacture
If fixed resistance values are used in delay circuits, then the circuit design is simplified, but the delay signals cannot be dynamically adjusted based on transmission data
Solution Approach 1:
The patent replaces fixed resistance values with a variable resistance circuit whose resistance can be dynamically adjusted based on transmission data. This dynamic adjustment capability allows the delay circuit to adapt to different communication conditions and data types, enhancing versatility while maintaining a relatively simple circuit structure through the use of a single variable resistance element rather than multiple fixed resistance circuits.
Solution Approach 2:
The patent changes the resistance parameter from a fixed value to a variable value that can be adjusted based on transmission data. This parameter change enables the delay circuit to dynamically modify its delay characteristics without fundamentally changing the circuit structure, thereby maintaining ease of manufacture while achieving adaptability.
Data Source
AI summary
A delay signal generation circuit includes first to nth (n representing a natural number equal to or larger than 2) delay circuits and first to nth output terminals. The delay signal generation circuit is configured such that, in a first mode, an input signal passes through the first to kth (k representing a natural number equal to or larger than 1 but equal to or smaller than n) delay circuits in order and reaches the kth output terminal, and in a second mode, the input signal passes through the kth to nth delay circuits in reverse order and reaches the kth output terminal.