Delay Stage Selection Circuit for PVT-Stable Clock Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delay circuits are prone to system operation errors due to variations in Process, Voltage, and Temperature (PVT) factors, causing inconsistent delay signal adjustments.
Innovation Solution
A delaying stage selecting circuit that samples and compares clock signals, uses memory units to store sampled values, and determines the appropriate delaying stage based on specific relations, generating a counting value to control the delayed clock signals, thereby selecting a suitable delay signal in real-time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay circuits are used to synchronize clock signals, then the circuit can generate delayed clock signals with different phases, but the delay amount changes due to PVT (Process, Voltage, Temperature) factors causing system operation errors
Solution Approach 1:
The patent pre-calculates and stores delay amounts for multiple delaying stages in a lookup table before operation. During runtime, the system only needs to select from pre-computed values based on detected PVT conditions, avoiding real-time calculation errors and ensuring accurate delay adjustment despite environmental variations.
Solution Approach 2:
The system detects actual PVT conditions and uses this feedback to select appropriate delay stages from multiple options. The phase detector continuously monitors phase differences and adjusts the selected delaying stage accordingly, creating a closed-loop system that compensates for PVT variations and maintains synchronization accuracy.
2Device complexity
If a single delay signal is selected to meet system requirements, then the circuit structure can be simple, but the delay amount changes due to external factors causing system operation errors
Solution Approach 1:
Instead of using a single delay stage, the patent divides the delay function into multiple discrete delaying stages (first delaying stage, second delaying stage, etc.), each with predetermined delay amounts. This segmentation allows the system to select different stages based on PVT conditions, improving reliability while keeping each individual stage relatively simple.
Solution Approach 2:
The system dynamically selects which delaying stage to use based on detected PVT conditions and phase differences. Rather than relying on a fixed single stage, the system can switch between multiple delay stages adaptively, maintaining accuracy across varying operating conditions without requiring complex continuous adjustment mechanisms.
Data Source
AI summary
A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first register for sampling the delayed clock signals according to a clock signal to generate sampled values; first memory units, wherein the first memory units are utilized to memorize the sampled values, and each of first memory unit outputs at least one of the sampled values according to a corresponding first selecting signal; a first selecting unit, for outputting the sampled values according to a second selecting signal; a determining module, for determining if the sampled values meet a specific relation, where if the determination result is positive then determining the particular delaying stage; and a counter for generating a counting value to control the delayed clock signal sampled by the first register.