Delay Synchronization Circuit Using One VCDL for Disturbance Suppression
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Solution Overview
Problem
Conventional delay synchronization circuits face a reduction in disturbance suppression due to differences in variable delay characteristics between first and second Voltage-Controlled Delay-Lines (VCDLs).
Innovation Solution
A delay synchronization circuit is designed with a pulse synthesizing circuit to generate synchronized signals, a signal delay circuit to delay these signals, a pulse separation circuit to separate the delayed signals, and a circulator to control the delay amount based on phase differences between reference and feedback signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay synchronization circuits use two separate VCDLs to delay reference and feedback signals, then the circuit can control delay amounts based on phase difference, but the variable delay characteristics between the two VCDLs do not completely match, causing reduced disturbance suppression
Solution Approach 1:
The patent merges the two separate VCDLs into a single VCDL that delays both the reference signal and the feedback signal. This ensures that both signals experience identical variable delay characteristics, eliminating the mismatch problem. The single VCDL is controlled by a delay control voltage generated from the phase difference between the reference signal and feedback signal, maintaining synchronization while ensuring consistent delay characteristics.
2Reliability
If a single VCDL is used to delay both reference and feedback signals, then variable delay characteristics match perfectly, but the circuit structure becomes more complex with additional signal processing components
Solution Approach 1:
The patent segments the signal processing into distinct functional blocks: a pulse synthesizing circuit that generates a synthesized signal from the reference signal and feedback signal, a single VCDL that delays this synthesized signal, and a pulse separation circuit that separates the delayed synthesized signal back into individual pulse signals. This segmentation maintains consistent delay characteristics while organizing the circuit complexity into manageable functional units.
Solution Approach 2:
The patent introduces a synthesized signal as an intermediary that combines both the reference signal and feedback signal before they enter the single VCDL. This synthesized signal serves as a mediator that allows both original signals to experience the same delay characteristics while maintaining their individual identities through the pulse separation circuit.
Data Source
AI summary
A delay synchronization circuit includes a pulse synthesizing circuit to generate a synthesized signal including a first pulse signal synchronized with a reference signal and a second pulse signal synchronized a feedback signal, a VCDL to delay the synthesized signal g and output a delayed synthesized signal, a pulse separation circuit to generate a first separation signal synchronized with a first pulse signal included in the delayed synthesized signal and generate a second separation signal synchronized with a second pulse signal included in the delayed synthesized signal, a circulator to output a first separation signal to a clock reception circuit and then output the first separation signal returned from the clock reception circuit to the pulse synthesizing circuit as the feedback signal, and a delay-amount control circuit to control a delay amount of the delayed synthesized signal according to a phase difference between the reference signal and the second separation signal.