Delay-Tap Clock Multiplier With Phase Detection for Stable Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock signal frequency adjustment techniques in digital circuits are prone to inaccuracies due to temperature and voltage fluctuations, and conventional frequency multipliers have high power and size requirements, making them unsuitable for compact devices like mobile telephone handsets.
Innovation Solution
A frequency multiplier circuit using serially connected delay elements and a phase detector to generate multiple clock signals with controlled phase shifts, enabling low-power and compact digital implementations suitable for mobile devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional frequency multipliers are used to generate multiple clock signals, then frequency multiplication is achieved, but power consumption and circuit size increase significantly
Solution Approach 1:
The frequency multiplier circuit is segmented into multiple delay elements connected in series, where each element contributes a portion of the total delay. This segmentation allows the circuit to achieve frequency multiplication through distributed delay rather than a single complex frequency multiplying stage, reducing overall power consumption while maintaining the frequency multiplication capability.
Solution Approach 2:
The circuit dynamically selects different delay elements based on the desired output frequency. By controlling which delay elements are activated and how their outputs are combined, the circuit can adaptively generate multiple clock signals at different frequencies without requiring separate frequency multiplier circuits for each frequency, thereby reducing total power consumption.
2Productivity
If conventional frequency multipliers are used to generate multiple clock signals, then frequency multiplication is achieved, but circuit area and complexity increase
Solution Approach 1:
The same delay element circuit serves multiple functions: it generates delay tap signals for phase detection, provides delayed signals for frequency multiplication, and enables duty cycle control. This multi-functionality eliminates the need for separate frequency multiplier circuits for different frequencies, significantly reducing the overall circuit area while maintaining full frequency multiplication capability.
Solution Approach 2:
The circuit merges the frequency multiplication function with the delay element structure. Instead of using separate frequency multiplier circuits, the delay elements themselves are configured to generate the multiplied frequency signals by combining their outputs based on detected phase shifts, thereby reducing circuit area.
3Adaptability or versatility
If existing clock signal frequency adjustment techniques are used, then frequency adjustment is possible, but duty cycle accuracy deteriorates due to temperature and voltage fluctuations
Solution Approach 1:
The circuit incorporates a feedback mechanism where the phase detector continuously monitors the phase relationship between the input clock signal and delay tap signals. Based on this feedback, the controller adjusts the selection of delay elements and their output combinations to maintain accurate duty cycles despite temperature and voltage fluctuations, ensuring stable frequency adjustment capability.
Solution Approach 2:
The circuit changes operational parameters dynamically by selecting different delay elements and adjusting their output weights based on detected phase shifts. This allows the circuit to compensate for temperature and voltage variations by adapting its internal delay characteristics, thereby maintaining duty cycle accuracy across varying operating conditions while preserving frequency adjustment capability.
Data Source
AI summary
Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled.