Delay Time Detection Circuit Using Sub-Scale Clocks for Accurate Stamping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay time detection circuits require phase synchronization and high-resolution timestamp functions, leading to increased circuit complexity and cost, which hinders the generation of high-accuracy time information.
Innovation Solution
A delay time detection circuit comprising a clock generation unit, a count unit, and a sub scale signal generation unit that calculates delay time within a first period using a sub scale clock signal, allowing for high-accuracy time information generation without the need for phase synchronization or high-resolution timestamp functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a circuit utilizes a first period corresponding to a main scale and a second period corresponding to a sub scale to improve stamping accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the time measurement function into two distinct periods: a first period (main scale) for coarse time measurement and a second period (sub scale) for fine time measurement. This segmentation allows the circuit to achieve high stamping accuracy by combining measurements from both periods while keeping the circuit structure manageable through functional division.
Solution Approach 2:
The patent introduces a temporal dimension by utilizing two different time periods (first period and second period) for measurement. By measuring time differences at two distinct time scales and combining these measurements, the circuit achieves higher precision without proportionally increasing complexity, effectively adding a dimensional approach to time measurement.
2Measurement precision
If a high-resolution timestamp function is included to improve time measurement accuracy, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent employs dynamic switching between two measurement modes corresponding to the first period and second period. Rather than using a static high-resolution timestamp function throughout, the circuit dynamically selects which period to use based on measurement requirements, achieving high accuracy when needed while maintaining simpler operation during normal conditions.
Solution Approach 2:
The patent changes the time period parameter between two discrete values (first period and second period) to achieve different measurement resolutions. By switching between these parameter values rather than continuously varying them or using a fixed high-resolution setting, the circuit achieves high measurement accuracy while controlling complexity through discrete parameter selection.
3Measurement precision
If phase synchronization is performed to improve time synchronization accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary measurement of time differences using the first period (main scale) before refining the measurement with the second period (sub scale). This preliminary action establishes a baseline time reference that simplifies subsequent precise measurements, reducing the overall complexity compared to performing full high-precision synchronization continuously.
Data Source
AI summary
A delay time detection circuit includes below configurations. A clock generation unit generates a sub scale clock signal, based on a system clock signal. A count unit generates a count signal while sequentially and repeatedly incrementing a count number, based on the sub scale clock signal. A sub scale signal generation unit receives the count signal, and generates sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with a second period and that are shifted in timing relative to one another according to the second period. A delay time calculation unit receives the input clock signal, and calculates a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals.