Ring Oscillator Clock Control Using Delay and Vdd Tuning
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Solution Overview
Problem
Existing low-power clock generators face challenges in rapidly converging to a frequency and voltage state that minimizes electrical consumption, especially under PVT variations.
Innovation Solution
A clock generator comprising a ring oscillator, a frequency detector, and a control circuit that adjusts the loop delay parameter and supply voltage based on feedback signals to regulate the output frequency, ensuring convergence to a low-power state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a control loop is used to regulate clock frequency for low-power operation, then power consumption is reduced, but the convergence speed to the optimal frequency and voltage state becomes slow
Solution Approach 1:
The control circuit performs preliminary actions by first adjusting the loop delay parameter to bring the output frequency close to the target frequency before engaging the supply voltage adjustment. This preliminary frequency alignment using the delay parameter creates a head start for the voltage regulation process, enabling faster convergence to the optimal low-power state without sacrificing accuracy
Solution Approach 2:
The control circuit dynamically switches between two control mechanisms: using loop delay parameter adjustment for rapid initial frequency correction, and supply voltage adjustment for fine-tuning and maintaining the target frequency. This dynamic switching strategy optimizes both convergence speed and power efficiency by applying the appropriate control method at each stage of the frequency regulation process
2Use of energy by moving object
If the supply voltage is reduced to minimize power consumption, then electrical consumption decreases, but the output frequency stability under PVT variations deteriorates
Solution Approach 1:
The control circuit changes multiple parameters in a coordinated manner: it adjusts both the loop delay parameter and supply voltage to achieve the target frequency while minimizing power consumption. By simultaneously optimizing these parameters rather than relying solely on voltage reduction, the system maintains frequency stability even at lower supply voltages, resolving the trade-off between power consumption and frequency stability under PVT variations
3Speed
If the loop delay parameter is reduced to increase output frequency, then frequency increases, but the power consumption increases
Solution Approach 1:
The control circuit dynamically selects between two methods to increase frequency: using loop delay parameter adjustment (which has minimal power impact) when possible, and supplementing with supply voltage adjustment only when necessary to reach the target frequency. This dynamic approach allows frequency increase while minimizing power consumption by relying primarily on the low-power delay parameter mechanism
Data Source
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AI summary
The present disclosure relates to a clock generator comprising: a ring oscillator (202) configured to generate an output frequency signal (F_RO); a frequency detector (204) configured to compare a frequency of the output frequency signal with r times a frequency of a reference frequency signal (f_REF) and to generate a feedback signal (a, a'); and a control circuit (210) configured to: control a loop delay parameter (τ) of the ring oscillator and a supply voltage (Vdd) of the ring oscillator based on the feedback signal; reduce the frequency of the output frequency signal when its frequency is higher than r times the frequency of the reference frequency signal by reducing the supply voltage; and increase the frequency of the output frequency signal when its frequency is lower than r times the frequency of the reference frequency signal by reducing the loop delay parameter.