Delayed High-Frequency Clock Circuits for EMI-Safe Spread Spectrum
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Solution Overview
Problem
Existing spread-spectrum clocking methods face challenges in effectively reducing Electro-Magnetic Interference (EMI) and ensuring reliable clock cycles, particularly in synchronous systems, where prior art techniques may miss clock cycles at low frequencies.
Innovation Solution
A method and circuit that delay a high-frequency clock signal to generate a plurality of delayed clock signals, which are pseudo-randomly selected using a multiplexer and fine delay adjustment circuit to create a spread-spectrum clock signal, ensuring clock edges are offset in time and reducing EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a phase-lock loop (PLL) is used to produce a spread-spectrum output, then EMI can be reduced by broad-banding the clock signal, but the system complexity and difficulty of detecting and measuring increase
Solution Approach 1:
The invention segments the clock signal generation into multiple parallel delay paths, each producing a delayed version of the input clock signal. These segmented paths are then combined through logical OR operations to generate the spread-spectrum clock output, avoiding the need for complex PLL circuits while maintaining EMI reduction benefits
Solution Approach 2:
The invention introduces an intermediary logic circuit that processes multiple delayed clock signals through OR gates and combination logic. This intermediary structure simplifies the detection and measurement of clock cycles by providing clear, well-defined transition edges that are easier to detect than PLL-generated spread-spectrum signals
2Object-affected harmful factors
If delay units are used to generate spread-spectrum clock signals, then EMI can be reduced, but clock cycles may be missed at low frequencies in synchronous systems
Solution Approach 1:
The invention dynamically adjusts the delay amounts in each path based on the input clock frequency. By making the delay values variable rather than fixed, the system maintains reliable clock cycle generation across a wide frequency range, preventing missed clock cycles at low frequencies while preserving EMI reduction at higher frequencies
Solution Approach 2:
The invention incorporates feedback mechanisms that monitor the input clock signal characteristics and adjust the delay circuit operation accordingly. This feedback ensures that the delayed signals maintain proper timing relationships, preventing clock cycle loss in synchronous systems while maintaining spread-spectrum EMI reduction
3Object-affected harmful factors
If the clock signal is broad-banded to spread energy over wider frequencies, then EMI is reduced, but the precision of clock timing is degraded
Solution Approach 1:
The invention applies local quality by ensuring that each individual delayed clock path maintains precise, well-defined edge timing characteristics. While the overall output is spread-spectrum, each local path preserves timing precision, allowing synchronous systems to reliably detect clock edges while still achieving EMI reduction through the combination of multiple delayed paths
Data Source
AI summary
A method of generating a spread-spectrum clock signal includes delaying a high frequency clock signal to provide a plurality of delayed high frequency clock signals selected among to provide a spread-spectrum clock signal for a synchronous system.