Integrated Clock Control for Pre-Mount Noise and Jitter Testing
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Solution Overview
Problem
Integrated circuits can fail due to system voltage noise or system clock jitter, which are typically detected only after mounting, causing delays in system development and making it difficult to identify failure sources.
Innovation Solution
An integrated circuit with a clock control unit that can selectively output a delayed or divided clock and a test mode signal generation unit to generate test mode signals, allowing for the simulation of system failures before mounting, thereby enabling pre-mount testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If system voltage noise or system clock jitter is detected only after the integrated circuit is mounted to the system, then the integrated circuit can be tested in the actual system environment, but a marked retardation in system development project occurs and it is difficult to find where a failure has occurred
Solution Approach 1:
The patent applies preliminary action by enabling failure detection functionality to be tested before the integrated circuit is mounted to the system. The test mode signal generation unit and clock control unit allow jitter and noise detection to be performed in advance during the manufacturing or testing phase, rather than waiting until system-level integration. This resolves the contradiction by detecting failures early (improving reliability assessment) while avoiding delays in system development (reducing time loss).
2Reliability
If a test mode is implemented with clock control unit to selectively output external clock or delayed clock, then pre-mount testing of system failures is enabled, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the clock control unit to perform multiple functions: it operates in normal mode during regular operation and switches to test mode when a test mode signal is received. The same clock control unit structure handles both external clock input and delayed clock generation, serving dual purposes. This resolves the contradiction by enabling pre-mount failure detection (improving reliability) while minimizing the increase in device complexity through multi-functional design.
Solution Approach 2:
The patent applies dynamics by making the clock control unit's behavior changeable based on the test mode signal. The clock control unit dynamically switches between normal operation mode and test mode, adjusting its functionality based on external control signals. This allows the same hardware structure to adapt to different testing requirements without permanent complexity increases, resolving the contradiction between pre-mount failure detection capability and device complexity.
3Reliability
If clock control unit generates divided clock and delayed clock for test mode, then system fail testing before mounting is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by implementing the clock control unit and test mode signal generation unit that enable failure detection functionality to be verified before the integrated circuit is mounted to the system. This allows manufacturers to test for jitter and noise-related failures during the manufacturing or packaging phase, identifying defective units before they reach the customer. This resolves the contradiction by enabling system fail detection capability (improving reliability) while allowing standard manufacturing processes to be used (maintaining ease of manufacture).
Data Source
AI summary
An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock.