Tri-State Driver Circuit Using Delayed Input for High-Impedance
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Solution Overview
Problem
Conventional tri-state driver circuits in high-speed integrated circuits require additional circuitry and power to manage a separate enable signal, leading to increased substrate area consumption and power usage due to complex timing coordination.
Innovation Solution
A signal driver circuit that provides automatic tri-state control without a separate enable signal, using a delay line and complementary transistors to manage logic levels and impedance states, allowing the true input signal and its complement to control the circuit's operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate enable signal is used to control the high-impedance state of the driver circuit, then the driver circuit can be tri-stated, but additional circuitry is required that consumes substrate area and electrical power
Solution Approach 1:
The patent merges the enable function with the existing data input circuitry. The enable signal is combined with the data signal path through logic gates (AND/OR gates) so that the same circuit elements that process data also control the tri-state function. This eliminates the need for separate enable signal circuitry and reduces substrate area while maintaining tri-state capability.
Solution Approach 2:
The patent makes the data input circuitry multi-functional by having it serve both data processing and enable control functions. The circuit elements process data signals during active periods and simultaneously generate enable control signals for the output stage, allowing one set of circuitry to perform multiple functions and reduce overall area.
2Adaptability or versatility
If a separate enable signal is used to control the high-impedance state of the driver circuit, then the driver circuit can be tri-stated, but additional circuitry is required that consumes electrical power
Solution Approach 1:
The patent merges the enable function with the existing data input circuitry. The enable signal is combined with the data signal path through logic gates (AND/OR gates) so that the same circuit elements that process data also control the tri-state function. This eliminates the need for separate enable signal circuitry and reduces substrate area while maintaining tri-state capability.
Solution Approach 2:
The patent makes the data input circuitry multi-functional by having it serve both data processing and enable control functions. The circuit elements process data signals during active periods and simultaneously generate enable control signals for the output stage, allowing one set of circuitry to perform multiple functions and reduce overall area.
3Adaptability or versatility
If a separate enable signal is used to control the high-impedance state of the driver circuit, then the driver circuit can be tri-stated, but complex timing coordination is required to prevent interference with output signal driving
Solution Approach 1:
The patent merges the enable function with the existing data input circuitry. The enable signal is combined with the data signal path through logic gates (AND/OR gates) so that the same circuit elements that process data also control the tri-state function. This eliminates the need for separate enable signal circuitry and reduces substrate area while maintaining tri-state capability.
Solution Approach 2:
The circuit automatically generates the enable control signal from the data input signals themselves through the logic gate combinations. The circuit serves itself by using its own input signals to control its output stage, eliminating the need for external enable signal generation and complex timing coordination circuitry.
Data Source
AI summary
Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.


