Delayed-Phase Frequency Detector for Wide Offset Detection
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Solution Overview
Problem
Conventional frequency detectors have a limited frequency detection range of about ±15%, leading to errors when detecting frequencies with offsets greater than 15%, especially due to PVT variations that can change the clock frequency by ±20%.
Innovation Solution
A frequency detector is designed with a first flip-flop to generate a first signal by sampling a clock signal based on a data signal, a second flip-flop to generate a second signal by sampling a delayed-phase component of the clock signal or the data signal, and a third flip-flop to generate a third signal representing the polarity of the frequency difference. A delay cell generates a delayed-phase component with a delay amount less than 0.25 Unit Interval (UI).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional frequency detector is used, then the device complexity is low, but the frequency detection range is limited to about ±15%
Solution Approach 1:
The frequency detector is divided into multiple independent flip-flop units (first, second, and third flip-flops) that each perform specific sampling functions. This segmentation allows the system to detect frequencies beyond the conventional ±15% range by combining outputs from multiple sampling paths, resolving the contradiction between extended detection range and device complexity.
Solution Approach 2:
The patent introduces a temporal dimension by using delayed-phase components of signals. By sampling at different time phases (current phase and delayed phase), the detector extends its detection capability beyond the traditional frequency offset limits, effectively adding a time-based dimension to the detection process.
2Reliability
If the frequency detection range is widened, then the reliability of frequency detection improves, but the device complexity increases
Solution Approach 1:
The third flip-flop receives inputs from both the first and second flip-flops and generates an output signal that represents the polarity of frequency difference. This feedback mechanism combines information from multiple sampling paths to produce a reliable frequency detection result, maintaining high reliability while managing system complexity through structured signal integration.
3Adaptability or versatility
If a delay amount greater than 0.25 UI is used, then the frequency detection range can be extended, but the probability of false outputs increases
Solution Approach 1:
The patent optimizes the delay parameter to be less than 0.25 UI (Unit Interval). This specific parameter setting allows the delayed-phase sampling to extend the detection range while maintaining sufficient timing resolution to avoid false outputs. The parameter optimization resolves the contradiction between detection range and measurement precision.
Data Source
AI summary
Disclosed is a frequency detector. The frequency detector includes a first flip-flop sampling a clock signal based on a data signal to generate a first signal, a second flip-flop sampling a delayed-phase component of the clock signal based on the data signal or sampling the clock signal based on a delayed-phase component of the data signal to generate a second signal, a third flip-flop generating a third signal representing a polarity of a frequency difference between a data rate of the data signal and a frequency of the clock signal based on the first signal and the second signal, and a delay cell generating the delayed-phase component of the clock signal or the delayed-phase component of the data signal. The delayed-phase component has a delay amount set to a value smaller than about 0.25 UI.