Pulse-Generated Level Shifter for Fast Low-Quiescent Transitions

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Solution Overview

Problem

Conventional level shifters face a trade-off between low quiescent currents and fast signal transitions, often consuming high static currents, which results in significant power loss, especially in gate driver circuits, while modern devices require lower quiescent currents and reduced propagation delays.

Innovation Solution

The proposed level shifter circuit incorporates a delay circuit, pulse generator, and latch circuit to generate short transitory signals, reducing quiescent power drain by activating current only during signal transitions, and utilizing logical AND circuits and switches to manage signal edges, thereby minimizing static quiescent currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional level shifters use continuous current to ensure fast signal transitions, then signal transition speed is improved, but quiescent current consumption increases

Engineering Contradiction:
Improvesignal transition speedVSAvoidquiescent current consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The level shifter uses periodic pulse signals generated from the input signal and its delayed version to activate the output transistor only during signal transitions. This periodic activation replaces continuous current flow, enabling fast transitions when needed while minimizing quiescent current consumption during stable states.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The circuit dynamically adjusts the output current based on the transition state of the input signal. During transitions, the circuit activates current flow to ensure fast switching; during stable states, it reduces current to micro-Amp levels. This dynamic behavior resolves the contradiction between speed and energy consumption.

Inventive Principle:
Principle #15Dynamics

2Loss of energy

If conventional level shifters reduce quiescent current to minimize power loss, then power consumption is improved, but signal transition speed decreases

Engineering Contradiction:
Improvepower lossVSAvoidsignal transition speed
Core Design Contradiction:
Loss of energyVSSpeed

Solution Approach 1:

By using periodic pulse generation based on signal edges, the circuit concentrates power consumption only during transitions rather than maintaining continuous current. This reduces overall power loss while ensuring sufficient current is available when fast transitions are required.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The circuit changes the current parameter dynamically - high current during transitions for fast switching, micro-Amp current during stable states for low power loss. This parameter modulation resolves the contradiction between power efficiency and transition speed.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If conventional level shifters use simple direct coupling between input and output, then device complexity is reduced, but propagation delay increases

Engineering Contradiction:
Improvecircuit structure simplicityVSAvoidpropagation delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The delay circuit generates a preliminary delayed version of the input signal before it reaches the pulse generator. This preliminary action creates the necessary timing conditions for generating sharp transition pulses, reducing propagation delay without requiring complex additional circuitry.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pulse generator acts as an intermediary between the input signal and output transistor, converting the input signal into optimized transition pulses. This intermediary function reduces propagation delay while keeping the overall circuit structure relatively simple.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4492684A1Level shifter circuit
Publication Date: 2025.01.15 NXP USA INC
  • EP4492684A1 patent drawingFigure 1
  • EP4492684A1 patent drawingFigure 2A~2B
  • EP4492684A1 patent drawingFigure 2C

AI summary

One example discloses a level shifter circuit, including: an input port configured to receive an input signal (IN); an output port configured to transmit an output signal (OUT); a delay circuit coupled to generate a delayed input signal (IN_DLY) from the input signal (IN); a pulse generator coupled to the delay circuit and configured to generate a pulse signal from a combination of the input signal and the delayed input signal; and a latch circuit coupled to the pulse generator and configured to generate and hold a state of the output signal in response to the pulse signal.