Delayed Read Indication for Asynchronous Processor-Accelerator Communication

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Solution Overview

Problem

In computing devices, processors face inefficiencies due to repeated polling for responses from accelerators performing computations, leading to increased power consumption and communication fabric traffic, as well as resource wastage and inability to perform other tasks while waiting for non-deterministic computation results.

Innovation Solution

Implementing a delayed read indication mechanism where the processor sends a delayed read request to an accelerator, allowing the result to be returned when the data value at a target memory location changes, enabling asynchronous communication and allowing the processor to perform other tasks during the waiting period.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processor repeatedly polls the accelerator for computation results, then it can determine when the computation is complete, but communication fabric traffic increases and power is wasted

Engineering Contradiction:
Improvedetermination of computation completionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

Instead of the processor actively polling the accelerator to check for completion, the completion status is pushed back to the processor through an interrupt mechanism. The accelerator generates an interrupt signal that automatically notifies the processor when computation is complete, inverting the traditional polling direction and eliminating wasted power from continuous checking.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The accelerator autonomously manages its own completion status by generating interrupt signals when computation finishes. Rather than requiring the processor to continuously query the accelerator, the accelerator self-services by automatically notifying the processor of its status changes, reducing communication overhead and power consumption.

Inventive Principle:
Principle #25Self-service

2Reliability

If the processor repeatedly polls the accelerator for computation results, then it can determine when the computation is complete, but communication fabric traffic increases

Engineering Contradiction:
Improvedetermination of computation completionVSAvoidcommunication fabric traffic
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The completion notification mechanism is inverted from active polling to passive interrupt-driven notification. Instead of the processor sending repeated read requests to check status, the accelerator sends a single interrupt signal when complete, dramatically reducing communication fabric traffic while ensuring reliable completion determination.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The completion status information is extracted and communicated through a separate interrupt channel rather than through repeated data read requests. This separates the status notification function from the data transfer function, allowing efficient communication of completion status without requiring repeated communication fabric transactions.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If the processor waits for computation results from the accelerator, then it can ensure proper data flow, but it cannot perform other tasks during the waiting period

Engineering Contradiction:
Improvedata flow controlVSAvoidprocessor throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The interrupt mechanism provides feedback to the processor when computation is complete, allowing the processor to maintain proper data flow control while not being blocked during the computation period. The processor can continue executing other tasks and will be notified via interrupt when the data is ready, eliminating idle waiting time.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The processor initiates the computation request and then immediately proceeds to execute other tasks without waiting for completion. The accelerator performs the computation in parallel, and the processor is notified in advance when the result is ready through an interrupt signal, allowing proactive task scheduling without compromising data flow integrity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10248331B2Delayed read indication
Publication Date: 2019.04.02 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10248331B2 patent drawing
  • US10248331B2 patent drawing
  • US10248331B2 patent drawing

AI summary

A requester sends, to a responding component, a request to cause the responding component to perform a computation. The requester sends, to the responding component, a delayed read indication, where the delayed read indication indicates that a result of the computation is not to be returned to the requester from the responding component until a data value at a target address of the delayed read indication has changed. The requester receives, from the responding component, an acknowledgment of the delayed read indication, and after receiving the acknowledgment, receives a response to the request without the requester sending another request to the responding component.