Duty Cycle Protection Circuit Using Delayed Reset Clock Correction
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Solution Overview
Problem
Clock signal distortion due to duty cycle asymmetry caused by local process variations and power supply noise, leading to potential signal stuck at logic low or high values during long-distance transmission across integrated circuits.
Innovation Solution
A duty cycle protection circuit comprising a synchronous device and reset circuitry that generates a second clock transition by resetting the synchronous device after a time delay, using pulse generation circuitry and a NAND gate to correct duty cycle distortion, with the reset circuitry coupled to the input line via the synchronous device or another synchronous device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the number of clock repeaters is increased to transmit the clock signal over long distances, then the clock signal transmission distance is improved, but duty cycle distortion worsens due to asymmetry between rising and falling transitions
Solution Approach 1:
The reset circuitry generates a reset pulse at a predetermined time delay after the first clock transition to proactively correct duty cycle distortion before it accumulates through multiple clock repeaters. This preliminary correction action prevents the distortion from propagating and worsening along the transmission line.
Solution Approach 2:
The reset circuitry monitors the clock signal transitions and applies corrective reset pulses based on detected transition timing. This feedback mechanism continuously adjusts the duty cycle to compensate for asymmetry introduced by process variations and power supply noise in the clock repeaters.
2Manufacturing precision
If conventional duty cycle correction circuits are implemented, then duty cycle distortion is reduced, but silicon area consumption increases
Solution Approach 1:
The reset circuitry is integrated with the existing clock repeater structure, combining the clock signal transmission function with the duty cycle correction function in a single compact circuit block. This merging eliminates the need for separate correction circuits and reduces overall silicon area consumption.
Solution Approach 2:
The clock repeater circuit performs multiple functions: it amplifies the clock signal to compensate for transmission losses and simultaneously applies duty cycle correction through the integrated reset circuitry. This multi-functionality reduces the total number of components needed and minimizes silicon area usage.
Data Source
AI summary
A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.