Delayed-Sampling ADC Circuit for Fast Switching Waveforms
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Solution Overview
Problem
Existing analog-to-digital converters face challenges in handling signal waveforms with radical changes during power device switching operations, requiring increased sampling rates while maintaining reduced circuit scale and costs.
Innovation Solution
The electronic circuit employs a configuration with delay elements, hold circuits, and a quantization circuit that uses different rising times for pulse signals to effectively sample and quantify input signals, allowing for high-speed sampling and analog-to-digital conversion without synchronizing sampling and quantization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling rate of the analog-to-digital converter is increased to handle signal waveforms with radical changes during power device switching, then the measurement precision and reliability improve, but the circuit scale and costs increase
Solution Approach 1:
The patent divides the analog-to-digital conversion process into multiple segments: a first ADC performs initial conversion at a lower sampling rate, and a second ADC performs additional conversion at a higher sampling rate only when radical changes are detected. This segmentation allows the system to achieve high measurement precision during critical switching events while maintaining reduced circuit complexity during normal operation.
Solution Approach 2:
The patent implements dynamic switching between different ADC operating modes based on the detected signal characteristics. When radical changes are detected in the signal waveform during power device switching, the system dynamically activates the second ADC to operate at higher sampling rate, and switches to the first ADC at lower sampling rate during stable periods, optimizing both precision and circuit resource utilization.
2Reliability
If the sampling rate is increased to capture rapid signal changes during power device switching, then the reliability of control improves, but the productivity and processing speed of the conversion system decreases due to increased data volume
Solution Approach 1:
The patent segments the high-reliability sampling process into two stages: the first ADC handles routine conversion at lower rates, while the second ADC handles only the critical high-rate sampling during switching events. This segmentation ensures reliability during important transitions while maintaining overall system productivity by avoiding continuous high-rate sampling of all signals.
Solution Approach 2:
The patent applies partial high-rate sampling only when necessary - specifically during power device switching events when radical changes occur. Instead of continuously operating at maximum sampling rate, the system uses excessive sampling capacity selectively during critical moments, ensuring reliability when needed while preserving productivity during normal operation.
Data Source
AI summary
According to one embodiment, an electronic circuit includes a first delay element, a second delay element, a first hold circuit and a quantization circuit. The first delay element obtains a first signal by delaying a first pulse signal. The second delay element obtains a second signal by delaying the first signal. The first hold circuit holds a first voltage of an input signal corresponding to the first signal. The second hold circuit holds a second voltage of the input signal corresponding to the second signal. The quantization circuit obtains a third signal and a fourth signal each with different rising times based on a second pulse signal, to quantize the first voltage based on the third signal, and to quantize the second voltage based on the fourth signal.