Delayed Snoop Cache Coherency for Multi-Cache Throughput
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Solution Overview
Problem
In multi-core coherent systems, maintaining data coherency while reducing memory access latency and maximizing shared memory throughput is challenging due to heterogeneous components with different cache structures and access types, leading to CPU stall overhead and reduced throughput.
Innovation Solution
Implementing a multi-core shared memory controller (MSMC) that manages cache coherency through delayed snoop operations, where local copies of data blocks are marked as delayed and acknowledged later, allowing parallel processing without immediate eviction, and using virtual channels for arbitration to reduce connection complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a coherent interconnect is added to maintain data coherency in multi-core systems, then data consistency is guaranteed, but the interconnect becomes an access bottleneck reducing memory throughput
Solution Approach 1:
The patent segments the cache coherency maintenance into two phases: a delayed snoop phase where coherence is deferred, and a subsequent validation phase. This segmentation allows memory accesses to proceed without immediate coherence checks, reducing interconnect bottleneck while maintaining eventual data consistency through the delayed snoop mechanism.
Solution Approach 2:
The patent performs preliminary memory allocation and data transfer before full coherence validation is completed. By allowing the memory controller to allocate and transfer data first, then performing snoop operations in the background, the system achieves higher memory throughput while still guaranteeing coherence through the delayed validation process.
2Loss of time
If cache components issue cache allocate accesses with critical line first request to reduce CPU stall overhead, then CPU stall overhead is reduced, but other CPU's stall overhead may be extended and shared memory throughput reduced
Solution Approach 1:
The patent introduces a memory controller as an intermediary that manages multiple CPU requests to the shared memory. The controller arbitrates between critical line first requests from different CPUs, allowing it to balance the urgent needs of one CPU against the overall throughput of the shared memory system, preventing any single CPU from monopolizing the memory interface.
Solution Approach 2:
The patent implements dynamic request handling where the memory controller can adjust the priority and timing of coherence operations based on current system state. Instead of rigid critical line first protocols, the system dynamically manages snoop operations and memory allocations to optimize both CPU stall reduction and overall memory throughput under varying workloads.
3Reliability
If serial fashion access handling is used to guarantee atomicity and data ordering, then data consistency is maintained, but the interconnect becomes an access bottleneck
Solution Approach 1:
The patent implements periodic or batched snoop operations instead of continuous serial coherence checks. By grouping coherence validation into periodic operations that occur after memory allocations are complete, the system maintains data consistency through structured validation cycles while significantly reducing the interconnect bottleneck caused by continuous serial arbitration.
Data Source
AI summary
Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.