Delayed Snoop Cache Coherency for False Sharing Threads
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Solution Overview
Problem
In multi-core coherent systems, maintaining cache coherency is challenging due to heterogeneous components with different cache structures and access attributes, leading to increased CPU stall overhead and reduced memory throughput, particularly in scenarios of false sharing where multiple cores operate on different segments of a cache line, necessitating serial snoop and evictions.
Innovation Solution
A method involving storing data blocks in a main cache memory, creating local copies on multiple processors, allowing processors to modify assigned blocks with write-through operations, transmitting invalidate requests, and marking delayed snoop for unmodified blocks, thereby reducing unnecessary evictions and optimizing memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial snoop and eviction operations are performed to maintain cache coherency in false sharing scenarios, then data consistency is guaranteed, but CPU stall overhead increases and memory throughput decreases
Solution Approach 1:
The patent segments the cache line into multiple regions, each associated with a different process. When a write operation occurs, only the specific region being modified is invalidated in other processors' caches, rather than invalidating the entire cache line. This regional segmentation allows concurrent access to different regions by different processes, maintaining coherency while enabling parallel operations and improving memory throughput.
Solution Approach 2:
The patent applies local quality by implementing fine-grained invalidation at the region level within a cache line. Each process has specific regions it can access, and invalidation is performed only for the affected region rather than the entire cache line. This localized approach reduces the scope of snoop operations and allows other processes to continue accessing their respective regions without interruption.
2Reliability
If serial snoop operations are performed to ensure data ordering and atomicity, then data correctness is maintained, but CPU stall overhead increases
Solution Approach 1:
The patent divides the cache line into multiple accessible regions for different processes. When a write operation occurs, the system performs snoop operations only on the specific region being modified rather than the entire cache line. This segmentation reduces the time required for snoop operations while maintaining data correctness through targeted invalidation of only the affected region in other processors' caches.
Solution Approach 2:
The patent implements partial action by performing snoop and invalidation operations only on the specific cache line region that is being modified, rather than performing full cache line operations. This partial approach reduces CPU stall overhead by minimizing the scope of coherence maintenance operations while still ensuring data correctness for the affected region.
3Reliability
If full cache line invalidation is performed to maintain coherency, then data consistency is ensured, but memory access latency increases
Solution Approach 1:
The patent segments the cache line into multiple regions with different access permissions for different processes. When a write operation occurs, only the specific region being modified is invalidated in other processors' caches, rather than invalidating the entire cache line. This regional approach reduces memory access latency by minimizing the scope of invalidation operations while maintaining data consistency through targeted coherence management.
Solution Approach 2:
The patent applies local quality by implementing region-specific invalidation within the cache line. Each process has defined regions it can access, and coherency is maintained by invalidating only the affected region rather than the entire cache line. This localized invalidation reduces memory access latency while ensuring data consistency for the modified region.
Data Source
AI summary
Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.