Delayed Strobe Generation for Semiconductor Data I/O Timing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As data transmission rates increase in semiconductor devices, issues such as line loading and skew differences between global input/output lines become significant, making it difficult to secure margins for transmitted data due to process changes.

Innovation Solution

A semiconductor device is designed with a strobing signal generating circuit that generates sequential write and read input/output signals based on delayed strobing signals, and an input/output control circuit that latches and processes data accordingly, ensuring accurate data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transmission rate is increased, then productivity is improved, but skew difference and line loading worsen

Engineering Contradiction:
Improvedata transmission rateVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by generating delayed versions of the strobing signal in advance before data transmission. The strobing signal generating circuit creates multiple delayed strobing signals (e.g., STB<0>, STB<1>, STB<2>, STB<3>) with different time delays before the actual data arrives. This preliminary preparation of timing references allows the receiver to accurately sample high-speed data despite skew differences and line loading effects, enabling higher data transmission rates while maintaining data integrity.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If data transmission rate is increased, then productivity is improved, but margin for transmitted data is reduced

Engineering Contradiction:
Improvedata transmission rateVSAvoiddata margin
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies dynamics by making the sampling timing adaptive rather than fixed. The receiver uses the delayed strobing signals to dynamically adjust its sampling points according to the actual arrival time of data bits. This dynamic timing adjustment allows the system to maintain adequate sampling margins even at high transmission rates where fixed timing would fail due to process variations and signal degradation.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If global input/output lines are used, then device complexity is reduced, but skew difference increases

Engineering Contradiction:
Improveinput/output line structureVSAvoidsignal timing accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces an intermediary element - the delayed strobing signal - to mediate between the global input/output lines and the data sampling process. The strobing signal generating circuit acts as an intermediary that receives the original strobing signal and produces multiple delayed versions that compensate for the timing skew introduced by the global lines. This intermediary mechanism allows the use of simple global I/O lines while maintaining timing accuracy through the intermediary delayed signals.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12412607B2Semiconductor devices related to data input and output operations
Publication Date: 2025.09.09 SK HYNIX INC
  • US12412607B2 patent drawing
  • US12412607B2 patent drawing
  • US12412607B2 patent drawing

AI summary

A semiconductor device includes a strobing signal generating circuit configured to sequentially generate write input signals, based on a write strobing signal and to sequentially generate write output signals, based on a delayed write strobing signal when a write operation is performed. The semiconductor device incudes an input/output control circuit configured to receive and latch write data input from a data input/output circuit, based on the write input signals, and to store the latched write data in a cell area as write core data, based on the write output signals.