Delayed Write Through Cache for False Sharing
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Solution Overview
Problem
In multicore or multiprocessor systems, false sharing occurs when threads on different processors modify variables on the same cache line, leading to cache line invalidation and performance degradation, which existing coherence protocols fail to address efficiently.
Innovation Solution
Implementing a separate and distinct delay write through cache (DWTC) for each processor, where cacheable write accesses are split into shareable and non-shareable operations, with shareable operations allocated only to the DWTC and non-shareable operations to the main cache, ensuring efficient data management and coherence without unnecessary write-throughs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single unified cache is used in multicore systems, then cache coherence can be maintained through traditional protocols, but false sharing occurs when threads on different processors modify variables on the same cache line, leading to cache line invalidation and performance degradation
Solution Approach 1:
The cache is segmented into two distinct parts: a main cache for non-shareable writes and a delayed write-through cache (DWTC) for shareable writes. This segmentation allows the system to handle different types of write operations separately, preventing false sharing invalidations in the main cache while maintaining coherence through controlled write-throughs in the DWTC.
Solution Approach 2:
The DWTC acts as an intermediary structure between the processor and the main cache. It buffers shareable write operations and manages their propagation to other caches, thereby preventing unnecessary invalidations in the main cache and reducing false sharing effects.
2Reliability
If traditional cache coherence protocols are used, then data consistency is maintained, but every write operation may trigger cache line invalidation and update across all caches, increasing energy consumption and reducing efficiency
Solution Approach 1:
Instead of performing full cache coherence updates for all write operations, the system applies partial action by routing only shareable writes through the DWTC with delayed write-throughs. Non-shareable writes are handled directly in the main cache without triggering system-wide coherence protocols, thereby reducing unnecessary energy consumption.
Solution Approach 2:
The system changes the timing parameter of write operations by introducing a delay mechanism in the DWTC. Shareable writes are buffered and propagated at optimized times rather than immediately, reducing the frequency of coherence updates and lowering energy consumption while maintaining data consistency.
3Device complexity
If shareable and non-shareable write operations are handled in the same cache, then cache structure is simple, but all write operations trigger the same coherence protocol, preventing optimization of false sharing scenarios
Solution Approach 1:
The cache is divided into two functional segments: main cache for non-shareable writes and DWTC for shareable writes. This segmentation enables different handling strategies for different write types, optimizing efficiency for both cases while maintaining manageable complexity through clear separation of duties.
Solution Approach 2:
Different quality attributes are applied to different parts of the cache system. The main cache is optimized for fast non-shareable writes with direct access, while the DWTC is optimized for shareable writes with delayed propagation. Each segment has tailored characteristics suited to its specific function.
Data Source
AI summary
A cache and a method for operating a cache are disclosed. In an embodiment, the cache includes a cache controller, data cache and a delay write through cache (DWTC), wherein the data cache is separate and distinct from the DWTC, wherein cacheable write accesses are split into shareable cacheable write accesses and non-shareable cacheable write accesses, wherein the cacheable shareable write accesses are allocated only to the DWTC, and wherein the non-shareable cacheable write accesses are not allocated to the DWTC.