Delta Pixel Array Scan Line Reduction for LCD Impedance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delta type pixel arrays in liquid crystal displays (LCDs) result in uneven wire impedances and increased complexity in wire arrangement, leading to difficulties in manufacturing, higher production costs, and reduced transmittance due to the need for additional source lines and larger thin film transistors (TFTs).
Innovation Solution
The proposed solution involves a pixel array where every two sub-pixel rows correspond to one scan line, reducing the number of scan lines by half and doubling the number of data lines to equalize wire impedances, thereby simplifying the wire arrangement and improving the aperture ratio and transmittance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the conventional delta type pixel array is used with one scan line per sub-pixel row, then each sub-pixel row can be independently controlled, but the number of scan lines increases and the wire arrangement complexity increases
Solution Approach 1:
The patent merges the control of two adjacent sub-pixel rows into a single scan line by utilizing the staggered arrangement of delta type pixels. Specifically, scan line GL1 controls both sub-pixel row 1 and sub-pixel row 2, while scan line GL2 controls sub-pixel row 3 and sub-pixel row 4. This combining approach reduces the total number of scan lines required while maintaining proper control functionality through the alternating connection pattern of data lines to different row groups.
2Ease of operation
If wire lengths of data lines are increased to connect distant sub-pixels, then all sub-pixels can be connected to data lines, but the wire impedance becomes uneven and frame resolution is affected
Solution Approach 1:
The patent segments the data lines into multiple groups (first group DL1, second group DL2, third group DL3, fourth group DL4) with different connection patterns. Data lines in the first group connect to sub-pixel rows 1 and 3, while data lines in the second group connect to sub-pixel rows 2 and 4. This segmentation creates alternating connection paths that balance the wire lengths and impedances across different sub-pixel rows, ensuring uniform frame resolution.
3Reliability
If the number of source lines is increased to match the number of data lines, then each data line can have its own source line, but additional production costs are introduced
Solution Approach 1:
The patent implements multi-functionality where a single source line serves multiple data line groups. Specifically, source line SL1 provides signals to both data line groups 1 and 2, while source line SL2 provides signals to data line groups 3 and 4. This universal approach allows one source line to control multiple data lines, reducing the total number of source lines required from 4 to 2 while maintaining proper signal distribution across all sub-pixel rows.
4Productivity
If TFT size is increased to improve charge efficiency, then charge efficiency improves, but aperture ratio decreases and transmittance decreases
Solution Approach 1:
The patent creates equipotential conditions by ensuring that sub-pixels in different rows (e.g., sub-pixel SP3 in row 2 and sub-pixel SP4 in row 4) experience similar wire lengths and impedances to their connected data lines. The alternating connection pattern ensures that sub-pixels in staggered rows are electrically equivalent, allowing for more uniform TFT sizing across the display panel without sacrificing charge efficiency, thereby maintaining better aperture ratio and transmittance.
Data Source
AI summary
A pixel array and a display panel with the pixel array are provided. The number of the scan lines used in the pixel array is reduced to half, while the number of data lines is doubled because every two sub-pixel rows correspond to one scan line in the pixel array. The wire impedances between the data lines and the pixel array are thus made the same. The aperture ratio of each sub-pixel is thereby increased and the size of the TFT in each sub-pixel is also reduced. The complexity in the wire arrangement of the pixel array is accordingly lowered to improve the transmittance of the display panel and make the frame resolution of the display panel more even.