Delta Retiming Logic Simulation Speed
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Solution Overview
Problem
Event-driven simulators in electronic design automation face significant runtime penalties due to the high number of delta cycles generated during simulation, which can be time-prohibitive, especially when only a limited number of signals and elements within a design are of interest, leading to inefficiencies in digital system simulation.
Innovation Solution
Delta retiming is employed to efficiently simulate logic designs by shifting delta delays from high-activity regions to low-activity regions and reducing delta delays in high fan-in to low fan-out areas, thereby reducing the number of delta cycles and events generated, thus enhancing simulation speed without compromising delta-accurate behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If event-driven simulation is used to achieve delta-accurate behavior, then simulation precision is improved, but simulation runtime increases significantly
Solution Approach 1:
The design is divided into regions of interest and non-interest regions. Event-driven simulation is applied only to regions of interest where delta-accurate behavior is needed, while other regions use less detailed simulation models. This segmentation allows the system to maintain high precision where necessary while reducing overall computational overhead and runtime.
Solution Approach 2:
Different simulation precision levels are applied to different parts of the design based on their importance. Regions containing signals of interest use full event-driven simulation with delta delays, while other regions use simplified models. This local differentiation maintains accuracy for critical signals while improving overall simulation efficiency.
2Measurement precision
If delta delays are placed in high-activity regions, then simulation accuracy is maintained, but number of delta cycles increases
Solution Approach 1:
Delta delays are extracted and removed from high-activity regions where they generate excessive events. Instead, the patent uses simplified delay models in these regions while maintaining full delta delay accuracy only in regions containing signals of interest. This extraction reduces the number of delta cycles without compromising the accuracy of critical signal behavior.
Solution Approach 2:
Instead of placing delta delays in high-activity regions to ensure accuracy, the patent inverts the approach by removing delta delays from these regions and concentrating them only where necessary for accuracy. This inversion reduces event generation while maintaining precision for critical signals.
3Measurement precision
If full event-driven simulation is applied to entire design, then comprehensive accuracy is achieved, but computational complexity increases
Solution Approach 1:
The design is segmented into regions requiring full event-driven simulation and regions that can use simplified models. This segmentation reduces the overall computational complexity by applying complex simulation only where necessary while using simpler models elsewhere.
Solution Approach 2:
Instead of applying full event-driven simulation to the entire design (excessive action), the patent applies it only partially to regions containing signals of interest. This partial application reduces computational complexity while maintaining sufficient accuracy for the design's verification goals.
Data Source
AI summary
Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.