Delta-Sigma ADC Delay Circuits for Higher Optical Sensor Sensitivity
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Solution Overview
Problem
Existing ΔΣ analog-to-digital converters in optical sensors face challenges in enhancing sensitivity without increasing photodiode size, shortening measurement time, or increasing sampling frequency, which leads to high current consumption and quantization errors.
Innovation Solution
Implementing a ΔΣ analog-to-digital converter with first to nth delay circuits and a signal processing circuit that processes digital signals with delay signals to enhance sensitivity without increasing sampling frequency or elongating measurement time, using a signal processing circuit to generate a signal value from the digital and delay signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of the photodiode is increased to enhance sensitivity, then the sensitivity of the optical sensor is improved, but the size of the optical sensor becomes remarkably large
Solution Approach 1:
The patent segments the signal processing function into multiple stages: the photodiode generates the analog signal, the ΔΣ ADC converts it to digital with oversampling, and then multiple delay circuits (first to nth delay circuits) process the digital signal separately before aggregation. This segmentation allows sensitivity enhancement through signal processing rather than physical size increase.
Solution Approach 2:
The patent replaces the mechanical approach of increasing photodiode size with an electronic signal processing system. Instead of enlarging the physical light-sensitive element, the system uses digital signal processing with delay circuits to enhance sensitivity, substituting mechanical enlargement with electronic processing.
2Measurement precision
If the sampling frequency is increased to enhance sensitivity, then the sensitivity of the ΔΣ analog-to-digital converter is improved, but the current consumption increases due to the need for large-scale circuits such as PLL circuits
Solution Approach 1:
The patent uses dynamic delay circuits that can be configured in different numbers (first to nth delay circuits) to achieve variable effective sampling rates. Instead of fixed high-frequency sampling requiring PLL circuits, the system dynamically adjusts the number of delay stages to match the required measurement precision, reducing current consumption.
Solution Approach 2:
The patent changes the sampling parameter from fixed high frequency to variable effective sampling rate achieved through configurable delay circuits. By changing the number of active delay stages rather than increasing clock frequency, the system achieves sensitivity enhancement without the current consumption penalty of high-frequency PLL circuits.
3Measurement precision
If the average of a plurality of signal values is calculated to obtain an ultimate signal value to enhance sensitivity, then the sensitivity is improved, but the measurement time elongates and quantization error increases
Solution Approach 1:
The patent performs preliminary actions by pre-processing the digital signal through multiple delay circuits before final aggregation. The delay circuits prepare multiple time-shifted versions of the signal in advance, allowing the aggregation circuit to compute the final value in a single operation rather than requiring sequential averaging over extended time periods.
Solution Approach 2:
The patent transforms the time-domain averaging problem into a parallel processing problem by introducing delay circuits that create multiple signal paths. Instead of sequentially averaging signals over time, the system processes multiple delayed versions simultaneously and aggregates them, effectively moving from a time-based solution to a spatial/parallel processing solution that reduces measurement time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves higher sensitivity with reduced quantization errors and without increasing sampling frequency or elongating measurement time, by generating a signal value from delayed digital signals, thus improving optical sensor performance.
Implementation Method 1
a current corresponding to the intensity of light received by a photodiode flows through the photodiode
Data Source
AI summary
An analog-to-digital conversion device includes: a ΔΣ analog-to-digital converter configured to convert an analog signal into a digital signal having a pulse width corresponding to a magnitude of the analog signal; first to nth delay circuits, the first delay circuit being configured to delay the digital signal to generate a first delay signal, the ith delay circuit being configured to delay an i−1th delay signal to generate an ith delay signal, where i is an integer equal to or greater than two and equal to or smaller than n, and where n is an integer equal to or greater than two; and a signal processing circuit configured to obtain a signal value corresponding to the magnitude, from the digital signal and the first delay signal to an nth delay signal.