Continuous-Time Delta-Sigma ADC Feedback for Jitter Tolerance
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Solution Overview
Problem
Current low power analog-to-digital converters (ADCs) with high dynamic range for electronic devices, such as wireless audio devices, struggle with clock jitter and signal aliasing issues, which reduces the robustness of these devices.
Innovation Solution
The proposed solution involves an integrated circuit with an ADC that includes a continuous time integrator, a digital-to-analog converter (DAC), and a switch circuit. The ADC generates an integration control signal based on the mode of the DAC, allowing for different integration times and configurations to address clock jitter and signal aliasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If current low power ADC designs are used, then power consumption is reduced, but clock jitter and signal aliasing issues occur which reduce robustness
Solution Approach 1:
The patent implements dynamic element matching (DEM) that randomly switches the connection of DAC elements to summing nodes based on a random bit sequence. This dynamic switching prevents deterministic timing errors from causing systematic distortion, thereby improving jitter tolerance and reducing signal aliasing while maintaining low power consumption through efficient current recycling
Solution Approach 2:
The patent changes the operational parameters of the DAC by varying the switching timing and random bit sequences according to the digital output values. This parameter variation ensures that feedback currents are properly timed and distributed, preventing clock jitter and signal aliasing issues that would otherwise degrade robustness in low power ADC designs
2Device complexity
If feedback current is not properly timed, then circuit complexity is reduced, but clock jitter and signal aliasing occur
Solution Approach 1:
The patent employs feedback mechanisms where the random bit sequence and switching timing are continuously adjusted based on the digital output of the ADC. This feedback ensures that feedback currents are properly timed and distributed to summing nodes, preventing clock jitter and signal aliasing without requiring overly complex external timing circuits
Solution Approach 2:
The ADC system generates its own random bit sequences and timing signals internally through the DEM circuitry. This self-service approach provides precise timing control for feedback currents without requiring external complex timing circuits, thereby maintaining low circuit complexity while preventing clock jitter and signal aliasing
3Reliability
If dynamic element matching is implemented, then jitter tolerance is improved, but device complexity increases
Solution Approach 1:
The patent segments the DAC into multiple independent elements that can be individually switched and matched. This segmentation allows the DEM circuitry to distribute feedback currents across multiple paths, improving jitter tolerance through statistical averaging while keeping each individual switch and control logic relatively simple
Solution Approach 2:
The patent uses periodic switching of DAC elements controlled by clock signals and random bit sequences. This periodic action with randomized phases distributes timing errors uniformly across the signal spectrum, improving jitter tolerance while maintaining regular, predictable circuit operation that avoids excessive complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the robustness of the ADC by improving jitter tolerance and reducing noise folding, while maintaining low power consumption and high linearity, thus enabling high fidelity audio processing in active noise cancellation applications.
Implementation Method 1
a capacitor coupled between the amplifier input and the amplifier output
Implementation Method 2
The continuous time integrator includes a capacitor that integrates a current over a time period to generate an integration output
Implementation Method 3
a resistor with a first resistor terminal configured to receive an analog input and a second resistor terminal coupled to the amplifier input. The resistor is configured to provide a first current for an integration
Implementation Method 4
an amplifier having an amplifier input and an amplifier output
Data Source
AI summary
Aspects of the disclosure provide an integrated circuit. The integrated circuit includes an ADC with a continuous time integrator. The continuous time integrator includes an amplifier having an amplifier input and an amplifier output, a capacitor coupled between the amplifier input and the amplifier output, and a resistor. The resistor provides a first current for an integration in response to an analog input. The ADC also includes a DAC configured to generate a second current at an DAC output based on a digital output of the ADC and includes a switch circuit with a first switch circuit terminal coupled with the DAC output and a second switch circuit terminal coupled with the amplifier input. The switch circuit is configured to couple the DAC output with the amplifier input for a summation of the second current with the first current for the integration based on an integration control signal.