Continuous-Time Delta-Sigma ADC With SMASH DAC Linearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in wideband applications due to non-linearities in multi-bit digital-to-analog converters (DACs), which lead to increased power consumption, parasitic capacitance loading, and harmonic distortion, especially in pipelined ADCs, where correcting sub-DAC non-linearities is complex and power-consuming.
Innovation Solution
A continuous-time delta-sigma ADC with a multi-bit quantizer and a sturdy multi-stage noise shaping (SMASH) DAC, incorporating a 1-bit or 1.5-bit digital delta-sigma modulator, allows for quantization noise modulation and subtraction in the analog domain, enhancing maximum stable amplitude and linearity without additional noise cancellation filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multi-bit DACs are used in delta-sigma ADCs to improve quantization noise performance and power efficiency, then signal-to-noise ratio and power efficiency are improved, but non-linearities and element mismatch cause degradation in linearity and require additional calibration complexity
Solution Approach 1:
The multi-bit DAC is segmented into multiple 1-bit or 1.5-bit sub-DACs, each controlled by a separate digital delta-sigma modulator. This segmentation eliminates non-linearity issues because 1-bit DACs have inherently perfect linearity, while still achieving multi-bit resolution through the parallel combination of multiple sub-DACs.
Solution Approach 2:
Digital delta-sigma modulators are introduced as intermediary components between the main quantizer and the 1-bit sub-DACs. These modulators distribute the multi-bit quantizer output across multiple 1-bit channels, enabling the system to achieve multi-bit performance with the linearity of 1-bit DACs.
2Measurement precision
If multi-bit quantization is used to reduce quantization noise and increase maximum stable amplitude, then signal-to-noise ratio and dynamic range are improved, but non-linearities in the multi-bit DAC feedback loop degrade the linearity of the DSM
Solution Approach 1:
The feedback DAC path is segmented into multiple independent 1-bit sub-DACs, each with its own digital delta-sigma modulator. This allows the system to maintain multi-bit quantization for noise performance while using 1-bit DACs for perfect linearity in the feedback loop.
Solution Approach 2:
Multiple copies of 1-bit DAC circuits are used instead of a single multi-bit DAC. Each 1-bit copy is perfectly linear, and their parallel operation achieves the resolution equivalent to a multi-bit DAC without suffering from element mismatch non-linearities.
3Productivity
If pipelined ADC architecture is used to achieve high aggregate sample rates, then conversion speed is improved, but correcting non-linearities in sub-DACs becomes complex and requires additional calibration circuits that increase power consumption
Solution Approach 1:
The sub-DAC in each pipelined stage is segmented into multiple 1-bit or 1.5-bit sub-sub-DACs. This segmentation eliminates the need for complex non-linearity correction because 1-bit DACs are inherently linear, simplifying the pipelined architecture while maintaining high sample rate performance.
Data Source
AI summary
In accordance with an embodiment, a continuous-time delta-sigma analog-to-digital converter (ADC) includes: a continuous-time loop filter having an input coupled to an input of the continuous-time delta-sigma ADC; a multi-bit quantizer coupled to an output of the continuous-time loop filter; a 1-bit or 1.5 bit digital delta-sigma modulator having an input coupled to an output of the multi-bit quantizer and an output coupled to an input of the continuous-time loop filter; and a multi-bit digital delta-sigma modulator configured to requantize quantization error of the 1-bit or 1.5-bit digital delta-sigma modulator and having an output coupled to the input of the continuous-time loop filter and to an input of the 1-bit or 1.5-bit digital delta-sigma modulator.