Continuous-Time Delta-Sigma ADC with Compact Loop Filter Feedback
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Solution Overview
Problem
Designing a continuous-time delta-sigma analog-to-digital converter that meets the requirements of wireless communication receivers, such as high linearity, dynamic range, and bandwidth, while minimizing chip area and optimizing signal processing stages.
Innovation Solution
Incorporating innovative designs for the loop filter, quantizer, digital-to-analog converter, and operational amplifier, including a loop filter with series integrators and feedback resistive elements, a quantizer with a comparing and processing circuit for error correction, a multi-bit switched-capacitor DAC with dynamic element matching, and an operational amplifier with current clamping circuits for improved bandwidth and gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional loop filter design is used, then basic filtering function is achieved, but resistor size is large and chip area is increased
Solution Approach 1:
The patent changes the fundamental parameter of feedback implementation from resistive to capacitive. By using feedback capacitors connected to the inverting inputs of integrators, the loop filter achieves the required filtering performance without relying on large resistors, thereby reducing chip area while maintaining manufacturing precision.
2Reliability
If more signal processing stages are added to improve linearity and dynamic range, then performance is improved, but device complexity increases
Solution Approach 1:
The integrators in the loop filter serve multiple functions simultaneously: they provide filtering, feedback, and signal processing in a single stage. This multi-functionality achieves the required linearity and dynamic range without adding separate signal processing stages, thereby improving reliability while controlling device complexity.
3Adaptability or versatility
If external analog components are integrated on-chip to reduce product size, then integration is improved, but ADC performance requirements become more stringent
Solution Approach 1:
The patent replaces traditional resistive feedback mechanisms with capacitive feedback and operational amplifier-based integrators. This substitution enables high-precision signal processing suitable for integrated ADCs, achieving the required linearity and bandwidth performance while supporting high-level integration of external analog components on-chip.
Data Source
AI summary
An exemplary continuous-time delta-sigma analog-to-digital converter includes a loop filter, a quantizer, a dynamic element matching circuit, a latch, and a digital-to-analog converter (DAC). The loop filter contains a plurality of integrators coupled in series, including a first integrator and a second integrator; a first positive feedback resistive element, placed in a first positive feedback path between a first output node of the second integrator and a first input node of the first integrator; and a first negative feedback resistive element, placed in a first negative feedback path between a second output node of the second integrator and a second input node of the first integrator. The quantizer is implemented using a domino quantizer. The DAC contains a plurality of DAC units each having a capacitive device, a resistive device, and a switch device coupled between the capacitive device and the resistive device.