Delta-Sigma ADC Comparator Offset Calibration for Multi-Bit Linearity
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Solution Overview
Problem
Conventional delta-sigma analog-digital converters suffer from comparator offset errors, which degrade conversion quality, especially in multi-bit resolution systems, and addressing this issue often requires complex circuitry or increased power consumption.
Innovation Solution
Incorporating a calibration device to determine and compensate for comparator offset errors at startup, allowing for simpler and power-efficient operation with high performance characteristics, including high-frequency signal handling and high-quality output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the quantiser has a plurality of comparators to deliver multiple bit resolution, then the converter resolution is improved, but the offset errors of multiple comparators degrade the conversion quality
Solution Approach 1:
The patent applies preliminary action by performing offset calibration of all comparators before the actual conversion operation. The calibration device determines offset errors of comparators at a predetermined point in time (before normal operation) and compensates for these errors in advance, ensuring high conversion quality when multiple comparators are used for multi-bit resolution
2Reliability
If comparator surface area and length are increased to reduce offset error, then the offset error is reduced, but the power requirement increases
Solution Approach 1:
The patent replaces the mechanical/physical approach of increasing comparator dimensions with a calibration-based electronic system. Instead of relying on larger transistor sizes to reduce offset errors, the invention uses a calibration device to measure and compensate offset errors through digital processing and feedback, achieving low offset error without the associated power penalty
3Reliability
If complex circuitry is added to reduce sensitivity to offset errors, then the converter quality is improved, but the device complexity increases
Solution Approach 1:
The patent introduces an intermediary calibration device that mediates between the comparators and the conversion process. This calibration device acts as a separate module that measures offset errors and generates compensation signals, rather than embedding complexity directly into the comparator circuitry itself, thus improving converter quality while maintaining relatively simple core circuit design
Data Source
AI summary
The invention concerns a time-continuous delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter for the filtering of the analog input signal, a clocked operated quantiser, which contains at least one comparator (34) and which quantises the filtered analog signal outputted through the analog filter for the generation of the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal. According to the invention a calibration device (32) linked with the quantiser is stipulated, which is designed to determine at a predetermined point in time an offset error of the comparator (34) and subsequently to compensate for this (Itrim).