Multistage Chopper-Stabilized Delta-Sigma ADC for Residual Offset Control
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Solution Overview
Problem
Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) face challenges in reducing residual DC offsets and 1/f noise due to mismatches in differential signal paths and chopping activities, which affect the accuracy of high dynamic range DC and low frequency measurements.
Innovation Solution
A multi-stage approach using both low and high chopping frequencies is implemented, with a series switch clocked at a relatively slow speed to up-convert the input signal to a low intermediate frequency, followed by demodulation to reduce the impact of residual errors and maintain accuracy without disturbing the error signal in the feedback loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional single-stage chopping is used to reduce DC offset, then offset reduction is achieved, but residual offsets and 1/f noise remain due to mismatches in differential signal paths
Solution Approach 1:
The patent divides the chopping operation into multiple stages with different chopping frequencies. A first chopper operates at frequency f1 and a second chopper operates at frequency f2, where f1 ≠ f2. This segmentation allows each chopping stage to address different components of the offset and noise, with the first stage reducing dominant DC offsets and the second stage addressing residual offsets and 1/f noise, thereby resolving the contradiction between initial offset reduction and residual accuracy.
2Measurement precision
If high frequency chopping is used to reduce offset, then DC offset is minimized, but sampling network mismatch effects and post-chopping residual offsets increase
Solution Approach 1:
The patent employs periodic chopping actions at two distinct frequencies. The first periodic chopping at frequency f1 reduces DC offsets, while the second periodic chopping at frequency f2 addresses the residual mismatch effects. By using multiple periodic actions with different frequencies, the system minimizes both DC offsets and sampling network mismatch effects simultaneously, resolving the contradiction between DC offset minimization and harmful mismatch effects.
3Measurement precision
If multi-stage chopping with different frequencies is implemented, then residual offsets and 1/f noise are reduced, but device complexity increases
Solution Approach 1:
The patent merges two chopping operations into a unified multi-stage chopping architecture. The first chopper and second chopper are integrated within the same ADC system, sharing common components such as the integrator and signal path. This merging approach reduces the overall complexity compared to implementing separate independent chopping systems, while still achieving residual offset and 1/f noise reduction through the coordinated action of multiple chopping stages.
Data Source
AI summary
A relatively low frequency chopping operation is applied to a delta-sigma ADC to reduce DC offsets resulting from non-ideal component operation. Sequential chopping takes place outside a closed loop and may include an inverted polarity feedback for a part of the chopping period. Nested chopping involves chopping within the closed loop, and may include an inverted polarity feedback and a time shift. The feedback compensation for sequential and nested chopping permits the correct polarity feedback to be provided at the desired time in conjunction with sampling and quantization events. Integrating capacitor(s) may be swapped in relative polarity during nested chopping to preserve residual conversion information for the desired polarity. The ADC operation is non-temperature dependent and avoids modification to the useful signal, resulting in higher accuracy.