Delta-Sigma ADC Intermittent Power-Down State
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Solution Overview
Problem
Delta-sigma analog-to-digital converters (ADCs) typically consume constant power across varying sample rates due to the need for continuous operation of the analog loop filter, making it inefficient to power down between conversions, especially at lower sample rates.
Innovation Solution
Implementing a power-saving mode by disabling digital clocks and analog portions of the converter between conversions, using a half-filter digital low-pass filter with a peak time-domain window function at the beginning of the response, and resetting the analog loop filter before each conversion to maintain stability and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the analog loop filter operates continuously to maintain conversion accuracy, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic operation of the analog loop filter by enabling it only during active conversion cycles and disabling it during idle periods. The filter is reset and re-enabled periodically according to the conversion rate, allowing the system to maintain accuracy when needed while consuming minimal power during idle times. This is achieved through control logic that manages the enable/disable states of the loop filter based on conversion timing.
2Use of energy by moving object
If the converter is shut down between sampling cycles to save power, then power consumption is reduced, but operation stability deteriorates
Solution Approach 1:
The patent applies preliminary action by resetting the analog loop filter before each conversion cycle begins. This reset operation prepares the filter in a known stable state prior to activation, ensuring stable operation when the filter is re-enabled. The reset occurs during the idle period before the next conversion, so when the filter becomes active again, it starts from a predetermined stable condition rather than an undefined state.
3Stability of the object's composition
If the analog loop filter is reset between conversions to maintain stability, then operation stability is improved, but conversion time increases
Solution Approach 1:
The reset operation is performed periodically and efficiently during the natural idle time between conversion cycles. The conversion time itself is maintained by keeping the filter active during the conversion window, while the reset occurs briefly in the gap between conversions. This periodic timing ensures that the filter is stable for the entire duration of each actual conversion operation, while the reset overhead is confined to the idle period and does not extend the critical conversion time.
Data Source
AI summary
A delta-sigma analog to digital converter (ADC) having an intermittent power down state between conversion cycles provides for power consumption savings when the converter is in a lower sample rate operating mode. Clocks provided to the digital portions of the converter are disabled, except for a periodic interval in which a conversion is performed at the higher selectable sample rate of the converter. The analog portions of the converter can also be disabled, but are re-enabled for a predetermined time period and reset before the digital clocks are enabled, so that the loop filter and feedback value supplied from the quantizer to the loop filter are stable prior to each conversion.