Delta-Sigma ADC Amplifier Switching for Lower Sensor Power
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Solution Overview
Problem
Switched-capacitor delta-sigma ADC circuits in digital sensors face high power consumption due to the need for multiple amplifiers to ensure proper settling at higher sampling rates, leading to increased quantization noise.
Innovation Solution
Implementing a dynamic bias current scheme that disables unnecessary amplifiers during the charge sampling phase and re-enables them during the charge redistribution phase, reducing power consumption while maintaining sufficient settling for higher signal-to-noise ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more amplifiers are enabled to ensure proper settling at higher sampling rates, then signal quality is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the amplifier configuration adaptive rather than static. The system dynamically adjusts the number of enabled amplifiers based on the operating sampling rate, using a logic circuit to select between different amplifier subsets (first subset for higher sampling rates, second subset for lower sampling rates) to optimize the balance between signal quality and power consumption at each operating point
Solution Approach 2:
The patent changes the operational parameters of the amplifiers based on sampling rate requirements. By modifying which amplifiers are enabled (a discrete parameter change) according to the sampling rate, the system achieves proper settling for different operating conditions while minimizing power consumption - enabling more amplifiers only when the higher sampling rate demands require the additional settling capability
2Measurement precision
If sampling rate is increased to improve signal-to-noise ratio through noise shaping, then signal quality is improved, but quantization noise dominates due to inadequate settling
Solution Approach 1:
The patent applies preliminary action by enabling the necessary amplifiers before the conversion process begins. The logic circuit pre-configures the appropriate number of amplifiers based on the intended sampling rate, ensuring that the integrator stages have sufficient settling capability prepared in advance before the actual signal conversion occurs, thereby preventing quantization noise dominance
3Reliability
If more amplifiers are continuously enabled to maintain settling at all sampling rates, then reliability is improved, but power consumption increases unnecessarily
Solution Approach 1:
The patent applies partial action by enabling only the necessary number of amplifiers required for each specific sampling rate rather than continuously enabling all amplifiers. The logic circuit determines the minimum sufficient configuration - using a first subset of amplifiers for higher sampling rates where more settling is needed, and a second subset for lower sampling rates where fewer amplifiers suffice, thereby avoiding excessive power consumption while maintaining adequate settling reliability
Solution Approach 2:
The patent implements periodic adjustment of amplifier enabling based on sampling rate changes. The logic circuit periodically re-evaluates and re-configures which amplifiers should be enabled according to the current operating sampling rate, ensuring that power consumption is optimized for each operating condition rather than maintaining a fixed high-power configuration
Data Source
AI summary
The disclosure relates to microphone and other sensor assemblies having a transduction element and an integrated circuit. The integrated circuit includes a switched-capacitor delta-sigma analog-to-digital converter (ADC) including a first integrator stage having a switched-capacitor circuit and a first plurality of parallel amplifiers. A logic circuit coupled to the integrator circuit is configured to selectably disable a subset of enabled amplifiers of the first integrator stage during a first phase of operation and to re-enable the subset of disabled amplifiers during a second phase.