Delta-Sigma D/A Conversion Timing Control for Jitter-Resistant Audio
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Solution Overview
Problem
Existing D/A converters face challenges in avoiding jitter influences without complex configurations, particularly when the center frequency of a PLL with a spread spectrum clock generator is not an integral multiple of the crystal oscillator's clock frequency, leading to potential data loss and leakage.
Innovation Solution
A digital-to-analog converter is configured to perform ΔΣ computation using a second clock signal whose frequency is higher than the first clock signal, with processes to determine and manage the computation based on integral multiples of clock periods, ensuring accurate conversion and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FIFO memory is used to absorb fluctuations of audio data due to periodic variation in the clock of the PLL with an SSCG, then data loss is reduced, but data leakage occurs and data is lost when there is no integral-multiple relationship between the center frequency of clocks and the crystal oscillator frequency
Solution Approach 1:
The patent applies dynamics by making the ΔΣ computation execution state changeable based on timing relationships between clocks. The system dynamically adjusts whether to execute ΔΣ computation by determining the relationship between the timing of the first clock (crystal oscillator) and second clock (PLL with SSCG), allowing flexible adaptation to different frequency combinations while maintaining data integrity through controlled computation execution.
2Adaptability or versatility
If the center frequency of the PLL with SSCG is set to avoid integral multiple of the crystal oscillator frequency, then frequency flexibility is improved, but it becomes difficult to set the center frequency and requires high-precision multiplication number
Solution Approach 1:
The patent applies parameter changes by utilizing the execution state of ΔΣ computation as a controllable parameter. By changing whether ΔΣ computation is executed or not based on the timing relationship between clocks, the system can adapt to different frequency combinations without requiring high-precision frequency setting, thus resolving the contradiction between frequency flexibility and precision requirements.
3Productivity
If ΔΣ computation is continuously executed based on the second clock signal, then conversion speed is improved, but data loss occurs when the computation timing does not align with the first clock signal
Solution Approach 1:
The patent applies feedback by using the timing relationship information between the first clock signal and second clock signal to control the execution of ΔΣ computation. The system determines whether to execute ΔΣ computation based on the relative timing of the two clocks, creating a feedback mechanism that ensures data integrity while maintaining efficient conversion by avoiding unnecessary computation or data loss scenarios.
Data Source
AI summary
A digital-to-analog converter performs a ΔΣ computation process to start the ΔΣ computation based upon the second clock signal with respect to the digital data of music sound if the ΔΣ computation is not under execution when the control signal is outputted by the signal output process, a control process to inhibit the ΔΣ computation based upon the second clock signal from being started with respect to the digital data of music sound until the ΔΣ computation is not under execution when the ΔΣ computation is under execution, and an output process to convert a computation result of the ΔΣ computation process into an analog signal and output the analog signal.