Delta-Sigma Modulator Chopper Clocking for Residue Noise Suppression
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Solution Overview
Problem
Chopper-stabilized delta-sigma modulators face challenges with high chopping residue noise and conversion errors due to fixed frequency chopping signals, which are not adequately suppressed by existing frequency-shaping techniques, and suffer from noise spikes caused by pseudorandom sequence wrap-around operations.
Innovation Solution
A delta-sigma modulator with a frequency-shaped pseudo-random chopper clock signal generator that includes a pseudo-random sequence generator automatically reset in synchronization with the digital output to prevent wrap-around noise, combined with a decimation filter to achieve low chopping residue noise levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed frequency chopping signal is used in a chopper-stabilized delta-sigma modulator, then the modulator can operate with stable clock timing, but chopping residue noise is converted to low frequency AC signal that degrades conversion accuracy
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed frequency chopping signal to a pseudorandom frequency chopping signal. The chopping frequency is dynamically varied according to a pseudorandom sequence, which prevents the conversion of offset voltage into a fixed low-frequency AC signal. This dynamic frequency variation spreads the chopping residue noise across a wider frequency spectrum, improving conversion accuracy while maintaining operational stability.
Solution Approach 2:
The patent changes the frequency parameter of the chopping signal from a fixed value to a pseudorandomly varying value. By modulating the chopping frequency according to a pseudorandom sequence, the system transforms the deterministic offset voltage conversion into a stochastic process, thereby reducing the magnitude of chopping residue noise at any specific low frequency and improving overall conversion accuracy.
2Measurement precision
If frequency-shaped pseudorandom chopping is applied to reduce chopping residue noise, then low frequency noise is reduced, but first order improvement is insufficient for very low noise applications
Solution Approach 1:
The patent employs periodic action through the use of a pseudorandom sequence with a finite period. The pseudorandom sequence generator produces a repeating sequence that periodically modulates the chopping frequency. This periodic modulation, combined with frequency shaping, achieves greater than first-order noise suppression by creating notches in the noise spectrum at frequencies corresponding to the periodicity of the pseudorandom sequence, thereby achieving very low noise levels required for high-precision applications.
3Ease of manufacture
If a finite length pseudorandom sequence generator is used, then the system can be implemented with practical circuitry, but wrap-around operation causes noise spikes that degrade performance
Solution Approach 1:
The patent applies beforehand cushioning by designing the pseudorandom sequence generator to complete full cycles before resetting. The sequence length and timing are carefully chosen so that the wrap-around point coincides with natural signal boundaries or low-frequency regions where the noise spikes have minimal impact on the band of interest. This pre-planned timing alignment cushions the system against the detrimental effects of wrap-around noise spikes, maintaining high measurement precision while using practical finite-length sequences.
4Measurement precision
If oversampling is used to improve conversion accuracy, then noise is averaged out, but the data output rate is reduced requiring complex decimation filtering
Solution Approach 1:
The patent applies dynamics by using pseudorandom frequency modulation of the chopping signal, which dynamically spreads the noise spectrum. This dynamic approach allows the system to achieve noise averaging benefits similar to oversampling without requiring as high an oversampling ratio. The pseudorandom frequency variation effectively increases the noise bandwidth, allowing for lower decimation ratios and higher data output rates while maintaining conversion accuracy.
Data Source
AI summary
A delta-sigma modulator includes a chopper-stabilized integrator, a quantizer having an input coupled to an output of the integrator, an input signal acquiring circuit controlled by a switched reference feedback circuit and having an output coupled to the input of the integrator, and a frequency-shaped pseudo-random chopper clock signal generator circuit including a pseudo-random sequence generator and producing a frequency-shaped pseudo-random clock signal. Resetting circuitry is coupled to reset inputs of the pseudo-random sequence generator to reset it in synchronization with the digital output of the chopper-stabilized delta-sigma modulator to prevent noise caused by wrap-around operation of the pseudorandom sequence generator. A logic circuit produces chopper clock signals in response to the frequency-shaped pseudo-random clock signal and applies them to various input switches and output switches of the integrator.