Delta-Sigma Converter Auto-Ranging for Fewer ADC Comparators
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Solution Overview
Problem
Existing delta-sigma analog-to-digital converters face challenges in high bandwidth applications, requiring high over sampling ratios that lead to high power consumption and large die size, especially in battery-powered devices like mobile phones, and struggle with stability under large interfering signals.
Innovation Solution
The implementation of auto-ranging logic within a delta-sigma modulator that dynamically shifts the digital output signal to counteract input variations, reducing power consumption and die size by operating within the ADC's mid-range region and incorporating a self-recovery technique to minimize the number of comparators needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high over sampling ratio (OSR) is used in a low order delta-sigma modulator for high bandwidth applications, then the required noise shaping is achieved, but the power consumption becomes excessively high
Solution Approach 1:
The patent implements dynamic element matching (DEM) that dynamically switches between different comparator configurations based on the input signal amplitude. The system transitions from a full multi-bit comparator array for small signals to a reduced configuration for large signals, optimizing power consumption while maintaining noise shaping performance across different operating conditions.
Solution Approach 2:
The patent changes the operational parameters of the delta-sigma modulator by dynamically adjusting the number of active comparators and their switching patterns based on signal characteristics. This parameter adaptation allows the system to achieve required noise shaping with lower power consumption by activating only the necessary number of comparators at any given moment.
2Measurement precision
If a high bit flash ADC is used to provide required noise shaping for high bandwidth applications, then the noise shaping is improved, but the power dissipation increases significantly
Solution Approach 1:
The patent employs dynamic element matching where the flash ADC's comparator array is dynamically reconfigured. Instead of continuously operating all comparators at full capacity, the system dynamically activates only the necessary subset of comparators based on the instantaneous signal amplitude, reducing power dissipation while maintaining the required noise shaping performance.
Solution Approach 2:
The patent extracts and utilizes only the essential portion of the flash ADC's comparator capability needed for the current signal conditions. By taking out and activating only the necessary number of comparators rather than operating the full high-bit ADC, the system achieves required noise shaping with significantly reduced power consumption.
3Use of energy by moving object
If a multi-bit delta-sigma modulator is used to reduce OSR and power consumption, then power efficiency is improved, but the die size increases due to the need for multiple comparators
Solution Approach 1:
The patent implements a dynamic reconfiguration mechanism that adjusts the active comparator subset based on signal requirements. The multi-bit delta-sigma modulator dynamically switches between different operational modes, activating only the necessary number of comparators for the current signal amplitude, thereby reducing the effective die size utilization while maintaining power efficiency benefits.
Solution Approach 2:
The patent segments the flash ADC's comparator array into multiple operational groups that can be independently activated. This segmentation allows the system to use only the necessary portion of the comparator array for any given signal condition, reducing the effective die size requirement while preserving the power efficiency advantages of multi-bit operation.
4Area of stationary object
If the number of comparators is reduced to minimize die size, then the die size is reduced, but the stability under large interfering signals deteriorates
Solution Approach 1:
The patent implements dynamic element matching that automatically adjusts the active comparator configuration in response to signal conditions. When large interfering signals are detected, the system dynamically activates additional comparators or switches to a configuration better suited for handling large signals, thereby maintaining stability and reliability while still achieving reduced die size under normal operating conditions.
Solution Approach 2:
The patent employs feedback mechanisms that monitor the input signal characteristics and adjust the comparator activation pattern accordingly. This feedback control ensures that when large interfering signals are present, the system automatically configures the comparator array to maintain stability, preventing signal distortion while still benefiting from reduced die size during normal operation.
Data Source
AI summary
An integrated circuit comprises a delta-sigma modulator incorporating a delta-sigma modulation loop having an analog-to-digital converter in a forward path and a digital-to-analog converter in a feedback path such that the ADC is arranged to receive samples of an analog input signal. The ADC is operably coupled to auto-ranging logic arranged to shift a digital output signal from the ADC representative of the analog input signal to counteract an effect of an input variation of the analog input signal. In this manner, the application of auto-ranging logic with a self-recovery technique supports a reduction of the number of comparators required in a multi-bit delta-sigma ADC.