Multi-Bit Delta-Sigma DAC Calibration for Mismatch Error Correction
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Solution Overview
Problem
Existing multi-bit Delta-Sigma modulators face performance limitations due to mismatch errors in the return digital-analogue converter, which are exacerbated by environmental conditions and aging, leading to reduced precision, increased power consumption, and degraded energy efficiency.
Innovation Solution
A calibration method for multi-bit Delta-Sigma modulators that adjusts the output level of active source cells using a matching signal generated from a calibration circuit, which processes the modulator's output signal and a calibration sequence to minimize mismatch errors, allowing calibration to be performed as a background task without interfering with the main operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If unit cells are dimensioned to minimize mismatch error, then precision is improved, but circuit size increases and speed decreases
Solution Approach 1:
The patent applies preliminary action by performing calibration of the digital-analogue converter's unit cells before normal operation. A calibration phase is introduced where test signals are applied and mismatch errors are measured, allowing correction values to be pre-computed and stored in lookup tables. This preliminary calibration eliminates the need for large, slow unit cells during normal operation, as the precision is achieved through pre-computed correction rather than physical cell size.
2Measurement precision
If DEM technique is used to average mismatch error noise, then linearity is improved, but latency increases and bandwidth decreases
Solution Approach 1:
The patent pre-computes correction values for mismatch errors during a calibration phase and stores them in lookup tables. During normal operation, these pre-computed corrections are applied directly without requiring dynamic element matching or averaging operations. This eliminates the latency introduced by DEM techniques while maintaining linearity improvement, as the corrections are prepared in advance rather than computed in real-time.
Solution Approach 2:
The patent replaces the mechanical switching and dynamic reconfiguration operations of DEM techniques with a static lookup table approach. Instead of dynamically interchanging unit cell selections to average out errors, the system uses pre-computed digital correction values that are applied through simple digital logic. This substitution of dynamic mechanical operations with static digital corrections reduces latency and eliminates the bandwidth limitations of DEM.
3Measurement precision
If calibration is performed at start-up, then mismatch error is corrected, but modulator must be in standby mode and correction is not robust to environmental changes
Solution Approach 1:
The patent implements periodic calibration where the modulator alternates between calibration mode and normal operation mode. During calibration, test signals are applied and correction values are updated to account for current environmental conditions. This periodic recalibration ensures that the system adapts to temperature drift, aging, and other environmental changes, maintaining precision without requiring the modulator to remain in permanent standby mode.
4Measurement precision
If pseudo-random signal is used for online correction, then mismatch error is detected, but dynamic range is reduced and power consumption increases
Solution Approach 1:
The patent performs mismatch error detection and correction during a preliminary calibration phase rather than continuously during normal operation. Test signals are applied once or periodically to measure mismatch errors, and correction values are stored for reuse. This eliminates the need for continuous pseudo-random signal injection, significantly reducing power consumption while maintaining detection precision. The correction values are prepared in advance and applied through simple digital lookup operations.
Data Source
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AI summary
Method for calibrating a multi-bit Delta-Sigma modulator comprising at least one main multi-bit digital-analogue converter in the return loop for generating a return signal subtracted from the input of the modulator, the main converter comprising a plurality of elementary source cells at least some of which, referred to as active cells, are associated with the various input bits of the converter for generating the return signal, the output level of these active source cells being adjustable under the action of a matching signal, the matching signal coming from a calibration circuit receiving an output signal from the modulator at its input, this calibration circuit comprising a generator of a calibration sequence.