Delta-Sigma DAC Error Cancellation With Lower-Order Analog Filtering
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Solution Overview
Problem
High-resolution digital-to-analog converters (DACs) require significant chip area, which increases exponentially with resolution, posing a challenge in minimizing footprint for high-resolution applications, especially in optical communications where multiple lanes are needed, such as in 100G×8 optical module-based and co-packaged optics solutions.
Innovation Solution
A delta-sigma modulator digital-to-analog converter with a multiple stage cascaded error cancellation architecture and an inverting amplifier-based analog filter is used, which reduces the filter order requirement and minimizes the analog filtering requirement, achieving a compact footprint by effectively canceling quantization noise and improving signal-to-noise ratio (SNR).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution DACs are used to achieve higher signal-to-noise ratio, then the SNR is improved, but the chip area increases exponentially
Solution Approach 1:
The high-resolution DAC is divided into multiple lower-resolution sub-DACs (e.g., two 8-bit DACs instead of one 10-bit DAC). Each sub-DAC handles a portion of the digital input words, and their analog outputs are combined. This segmentation allows achieving high effective resolution while each individual DAC occupies minimal area, thus resolving the exponential area growth problem.
Solution Approach 2:
A digital delay element is introduced as an intermediary between the digital input and the sub-DACs. The delay element stores one or more previous digital input words and provides them to the sub-DACs at appropriate timing. This intermediary enables the time-interleaved operation of multiple lower-resolution DACs to achieve higher effective resolution without requiring a single large high-resolution DAC.
2Adaptability or versatility
If multiple DACs are added to support more lanes in optical communications, then the number of lanes is increased, but the total chip area increases
Solution Approach 1:
The same high-resolution DAC architecture using multiple sub-DACs and digital delay elements is designed to be universally applicable across multiple optical communication lanes. Rather than implementing separate high-resolution DACs for each lane, the architecture can be shared or reused across lanes, allowing the system to support increased number of lanes (e.g., 100G×8) while minimizing the total chip area dedicated to DAC functionality.
3Ease of operation
If Nyquist-rate DACs are used for signal processing, then the signal processing function is achieved, but the chip area increases significantly with resolution
Solution Approach 1:
The Nyquist-rate DAC is segmented into multiple lower-resolution sub-DACs operating in parallel or time-interleaved fashion. Each sub-DAC processes a portion of the signal at the required Nyquist rate, but with reduced resolution requirements. The combined output achieves the necessary signal processing function with high effective resolution while each sub-DAC occupies minimal area, thus maintaining ease of operation without significant area penalty.
Data Source
AI summary
An apparatus includes a delta-sigma modulator digital-to-analog converter section having a multiple stag cascaded error cancellation architecture, each stage including a delta-sigma modulator followed by a digital-to-analog converter, the delta-sigma modulator digital-to-analog converter section configured to receive a digital input and to generate an analog output. An inverting amplifier-based analog filter is coupled to receive the analog output, the inverting amplifier-based analog filter configured to filter the analog output to produce a filtered analog output.