Delta-Sigma DAC Mismatch Shaping for Higher Linearity
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Solution Overview
Problem
Conventional Digital to Analog Converters (DACs) face limitations in linearity and accuracy due to mismatch in analog elements, leading to a practical limit on the maximum achievable number of bits, and increasing element size results in large designs.
Innovation Solution
A system utilizing a single-bit delta-sigma modulator (DSM) to convert lower LSBs, combined with dynamic element matching (DEM) and a P-element DAC, followed by low-pass filtering to improve linearity and accuracy, reducing the number of elements and incorporating noise shaping and element selection algorithms to minimize mismatch errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of analog elements is increased to improve linearity and ENOB, then linearity and accuracy are improved, but the design size becomes large and practical limits are reached
Solution Approach 1:
The DAC is divided into multiple sub-DACs, each with fewer elements. The digital input is segmented into multiple portions that are separately converted by each sub-DAC, and the analog outputs are summed. This segmentation allows achieving high resolution without requiring a single large array of analog elements.
Solution Approach 2:
The patent transitions from a single-bit DAC architecture to a multi-bit DAC architecture by adding temporal dimension through multiple conversion cycles. The digital input is processed in multiple bits per cycle, and the analog outputs are combined with appropriate weighting, achieving high resolution without proportionally increasing the number of analog elements.
2Measurement precision
If multiple analog elements are used to achieve higher bit resolution, then the maximum achievable number of bits is improved, but mismatch in analog elements causes non-linearity
Solution Approach 1:
The patent incorporates calibration circuits that measure the actual weights of analog elements and use this information to correct for mismatches. Digital correction codes are generated based on measured element characteristics, and these corrections are applied during conversion to compensate for manufacturing variations and maintain linearity.
Solution Approach 2:
The patent dynamically adjusts the weighting of individual analog elements based on their measured characteristics. By changing the effective parameter (weight) of each element through digital correction, the system compensates for manufacturing mismatches and maintains accurate linearity across the full dynamic range.
Data Source
AI summary
A system and method of digital to analog conversion including modulating a digital value DN−K with an oversampling delta sigma modulator to provide an M-bit coarse quantized value DM, in which DN−K comprises N−K least significant bits of an N-bit digital input value DN and in which quantization error may be shaped to a higher frequency above a signal band of interest, adding DM to a value DK to provide a select value DKM in which DK includes the K remaining most significant bits of DN, and applying mismatch shaping of a total of at least P=2K elements of a P-element DAC per cycle based on DKM to provide an analog output value. The analog output value may be filtered with a low-pass filter to provide a filtered analog output value. An order of low-pass filtering may be one more than an order of modulating.