Delta-Sigma Modulator Feedback DAC Split for Nonlinearity Suppression
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Solution Overview
Problem
Existing multi-bit delta-sigma modulators face challenges in suppressing circuit errors caused by non-linearity in multi-bit digital-to-analog converters (DACs), which cannot be effectively addressed by spectral shaping, especially in high-order modulators, and require complex digital algorithms that are not suitable for high-speed applications.
Innovation Solution
A multi-bit delta-sigma modulator design that incorporates a ternary DAC in the feedback path, combined with an (N−1)-bit DAC and additional feedback paths, to generate feedback signals, thereby reducing non-linearity errors and improving stability, using a combination of summation, integration, and filtering circuits to process signals and suppress circuit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-bit DAC is used in delta-sigma modulator, then quantization precision is improved, but circuit non-linearity errors increase
Solution Approach 1:
The patent segments the multi-bit feedback DAC into multiple sub-DACs, each handling a specific bit weight. This segmentation allows independent optimization and calibration of each sub-DAC, reducing the cumulative non-linearity errors while maintaining the benefits of multi-bit quantization precision.
Solution Approach 2:
The patent introduces an error correction mechanism that acts as an intermediary between the multi-bit DAC and the feedback path. This intermediary processes and compensates for non-linearity errors, allowing the system to maintain high quantization precision while suppressing harmful circuit errors.
2Measurement precision
If high-order modulator is used, then spectral shaping capability is improved, but stability deteriorates
Solution Approach 1:
The patent employs multiple feedback paths with carefully designed feedback filters that provide stability compensation. The feedback mechanism monitors and corrects deviations in real-time, allowing high-order spectral shaping while maintaining system stability through active compensation.
Solution Approach 2:
The patent dynamically adjusts feedback filter parameters and gain settings based on operating conditions. This parameter adaptation allows the modulator to maintain optimal stability margins while achieving aggressive spectral shaping performance across different signal levels and frequencies.
3Object-generated harmful factors
If complex digital algorithms are used to suppress circuit errors, then error suppression is improved, but processing speed deteriorates
Solution Approach 1:
The patent replaces complex iterative digital error correction algorithms with an optimized analog error correction circuit. This substitution uses dedicated hardware logic and analog processing to achieve error suppression without the computational overhead that would limit processing speed.
Solution Approach 2:
The patent implements preliminary calibration and error characterization during manufacturing, storing correction tables in on-chip memory. During operation, pre-computed correction values are applied directly without real-time computation, achieving error suppression while maintaining high processing speed through lookup table-based correction.
Data Source
AI summary
An N-bit delta-sigma modulator reduces circuit errors associated with an internal N-bit digital-to-analog converter by replacing the N-bit digital-to-analog converter with a digital feedback circuit comprising a ternary digital-to-analog converter and an (N−1)-bit digital-to-analog converter. The internal N-bit digital-to-analog converter is typically used to generate a global feedback signal that is provided to a first summation circuit. To provide an equivalent function but with better noise transfer characteristics, the digital feedback circuit generates two feedback signals. The ternary digital-to-analog converter is part of a first feedback path that generates a first feedback signal for the first summation circuit, and the (N−1)-bit digital-to-analog converter is part of a second feedback path that generates a second feedback signal for the first summation circuit or a subsequent summation circuit.