Delta-Sigma ADC Double Sampling for High SNR at Lower Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Delta-Sigma modulators face challenges in achieving high signal-to-noise ratio and dynamic range while minimizing power consumption and complexity, particularly due to the limitations of single-bit comparators and the need for increased sampling rates.
Innovation Solution
The proposed electronic device employs a fully differential architecture with a first switched capacitor integration stage that uses double sampling and random selection of reference feedback capacitors, along with a chopper principle to reduce power consumption and eliminate non-linearities, thereby improving signal-to-noise ratio and dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling rate is increased to improve dynamic range and signal-to-noise ratio, then the achievable dynamic range increases, but the power consumption increases
Solution Approach 1:
The patent implements double sampling where the first switched capacitor integration stage performs sampling at twice the frequency of subsequent stages. This periodic action at different rates allows the system to achieve the benefits of high sampling rates for noise shaping while reducing the average power consumption by having only one stage operating at the higher frequency
Solution Approach 2:
The modulator is segmented into multiple integration stages with different sampling rates. The first integration stage operates at a higher sampling rate than the second stage, allowing each stage to be optimized for its specific function while collectively achieving the desired signal-to-noise ratio with reduced overall power consumption
2Measurement precision
If the order of the Delta-Sigma modulator is increased to improve dynamic range, then the achievable dynamic range increases, but the complexity increases
Solution Approach 1:
The patent changes the sampling rate parameter of the first integration stage to be twice that of the second stage. This parameter change allows the modulator to achieve higher dynamic range through noise shaping without proportionally increasing the number of integrators or overall system complexity
Solution Approach 2:
The system employs dynamic sampling rates across different integration stages rather than a uniform sampling rate. The first stage dynamically operates at a higher rate to capture more signal information, while subsequent stages operate at lower rates, creating a dynamic architecture that achieves high dynamic range with manageable complexity
3Reliability
If a single-bit comparator is used to maintain robustness and linearity, then the linearity is maintained, but the signal-to-noise ratio is limited
Solution Approach 1:
The patent employs feedback in the Delta-Sigma modulation architecture where the quantization error from the single-bit comparator is fed back through the integration stages. This feedback mechanism, combined with noise shaping, allows the system to achieve high signal-to-noise ratio despite using a simple single-bit comparator that maintains excellent linearity
Solution Approach 2:
The first integration stage performs preliminary integration of the quantization error at a higher sampling rate before it is processed by subsequent stages. This preliminary action shapes the noise spectrum in advance, pushing quantization noise to higher frequencies where it can be filtered out, thereby improving the in-band signal-to-noise ratio while maintaining the simplicity and linearity of the single-bit comparator
Data Source
AI summary
The modulator comprises a first and second integration stages, and a comparator, the first integration stage is fully differential having: an amplifier, sets of input sampling capacitors and feedback capacitors, and the first integration stage is configured to sample the analog input voltage on a set of input capacitors during a first portion of a clock cycle and on a set of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a set of feedback capacitors during the first portion of the clock cycle and on a set of feedback capacitors during the second portion of the clock cycle, and the first set of feedback capacitors and the second set of feedback capacitors are randomly selected out of the plurality of sets of feedback capacitors from cycle to cycle.