Delta-Sigma ADC Digital Filter With Phase-Shifted Differentiators
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Solution Overview
Problem
Delta-sigma analog-to-digital converters face a tradeoff between oversampling ratio (OSR) and noise, where higher OSR reduces noise but decreases output data rate, and lower OSR increases noise but enhances data rate, limiting the ability to achieve both low noise and high data rate simultaneously.
Innovation Solution
The implementation of a filter with multiple stages of integrators and differentiators, including a results circuit and clock circuit that generates phase-shifted clocks, allows for increased data rate while maintaining low noise by decimating the output at a higher rate than conventional sinc filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the oversampling ratio (OSR) is increased to reduce noise, then the noise level decreases, but the output data rate decreases
Solution Approach 1:
The filter is divided into multiple parallel differentiator circuits (first differentiator circuit and second differentiator circuit) that process data simultaneously. Each differentiator circuit operates independently on the integrated data, allowing the system to produce multiple output streams in parallel, thereby increasing the overall output data rate without requiring a reduction in OSR
Solution Approach 2:
The differentiator circuits are clocked with phase-shifted clocks that are out of phase with respect to each other. This periodic action with different phases allows each differentiator to operate at optimal timing, enabling higher data throughput while maintaining the noise reduction benefits of the higher OSR
2Productivity
If the oversampling ratio (OSR) is decreased to increase output data rate, then the output data rate increases, but the noise level increases
Solution Approach 1:
The integrator circuit performs preliminary integration of the modulator output data before it is distributed to the multiple differentiator circuits. This preliminary action of integration establishes a foundation that allows subsequent differentiation to occur at higher rates without introducing excessive noise, as the integration has already processed and stabilized the input signal
Data Source
AI summary
An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.