Delta-Sigma ADC Digital Filter With Phase-Shifted Decimation
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Solution Overview
Problem
Delta-sigma analog-to-digital converters face a tradeoff between oversampling ratio (OSR) and noise, where higher OSR reduces noise but decreases output data rate, and lower OSR increases noise but enhances data rate, limiting the ability to achieve both low noise and high data rate simultaneously.
Innovation Solution
The implementation of a filter with multiple stages of integrators and differentiators, including a results circuit and clock circuit that generates phase-shifted clocks, allows for increased data rate while maintaining low noise by decimating the output at a higher rate than conventional sinc filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If oversampling ratio (OSR) is increased to reduce noise, then noise is reduced, but output data rate decreases
Solution Approach 1:
The filter is divided into multiple parallel differentiator circuits (first differentiator circuit and second differentiator circuit) that process data simultaneously. Each differentiator circuit operates independently with its own clock signal, allowing parallel processing of modulator data and doubling the effective output data rate while maintaining the noise reduction benefits of high OSR
Solution Approach 2:
The patent uses phase-shifted clock signals to periodically activate different differentiator circuits. The first clock signal clocks the first differentiator circuit during one phase, while the second clock signal (out of phase with the first) clocks the second differentiator circuit during another phase. This periodic switching between parallel circuits enables higher effective data rate without increasing noise
2Productivity
If oversampling ratio (OSR) is decreased to increase output data rate, then output data rate increases, but noise increases
Solution Approach 1:
By segmenting the filter into multiple parallel differentiator circuits that can be activated alternately, the system achieves higher effective output data rate without reducing the oversampling ratio. The parallel structure allows the ADC to process and output data faster while each individual differentiator maintains the noise filtering characteristics of the high OSR configuration
Solution Approach 2:
The patent dynamically switches between different differentiator circuits using phase-shifted clock signals. This dynamic activation allows the system to adapt the effective data rate by controlling which circuits are active at different times, achieving high output data rate performance while maintaining low noise through the high OSR filtering action in each circuit
Data Source
AI summary
An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.