Delta-Sigma Modulator Filter-Order Switching for Lower Power
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Solution Overview
Problem
Existing delta-sigma modulators face challenges in reducing circuit area and current consumption while maintaining high Signal-to-Noise Ratio (SNR) due to the need for higher-order filters, which increases the number of operational amplifiers and power consumption.
Innovation Solution
A delta-sigma modulator design that switches filter order by using feedback circuits with charge holding circuits operating at double sampling timing, allowing the filter characteristic to shift between zero-point shift and no zero-point shift, reducing the number of operational amplifiers and relaxing settling accuracy without deteriorating SNR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If higher-order filters are used to maintain high SNR, then filtering performance is improved, but the number of operational amplifiers increases and power consumption increases
Solution Approach 1:
The patent implements dynamic filter order switching by controlling switches in feedback circuits based on signal bandwidth detection. The filter transitions between different orders (e.g., 5th order for wideband, 3rd order for narrowband) to match operational requirements, avoiding the need to maintain high-order filter components continuously and reducing power consumption when full filtering capability is not needed.
Solution Approach 2:
The patent changes the filter order parameter dynamically based on signal characteristics. By detecting signal bandwidth and adjusting the filter order accordingly, the system optimizes the balance between SNR performance and power consumption, using higher filter orders only when necessary for narrowband signals requiring high SNR.
2Measurement precision
If higher-order filters are used to maintain high SNR, then filtering performance is improved, but circuit area increases
Solution Approach 1:
The patent uses dynamic filter order switching to reduce circuit area. By implementing switches that can bypass certain filter stages based on signal bandwidth requirements, the physical filter components are shared between different filter orders. This allows the circuit to achieve high-order filtering performance only when needed, while occupying less area when lower-order filtering suffices.
Solution Approach 2:
The patent designs feedback circuits where the same physical components serve multiple filter order functions. The feedback circuits can be configured to provide different filter orders (e.g., contributing to 3rd order or 5th order filtering) based on switch positions, making the circuit elements universal and reducing the total component count required for supporting multiple filter orders simultaneously.
3Use of energy by moving object
If the number of operational amplifiers is reduced, then power consumption decreases, but filter order reduction deteriorates SNR
Solution Approach 1:
The patent dynamically adjusts the number of active operational amplifiers based on signal bandwidth requirements. For wideband signals where high SNR is less critical, fewer amplifiers are activated, reducing power consumption. For narrowband signals requiring high SNR, the full complement of amplifiers is activated to provide the necessary filtering performance, thus dynamically optimizing the power-SNR tradeoff.
4Use of energy by moving object
If filter order is switched to reduce operational amplifiers, then power consumption decreases, but settling accuracy may be affected
Solution Approach 1:
The patent implements preliminary settling time allocation based on filter order selection. When switching to lower-order filters, the system adjusts the settling time period accordingly, ensuring that the reduced number of operational amplifiers have sufficient time to settle before signal processing continues. This preliminary timing adjustment prevents settling accuracy degradation while maintaining power savings from reduced amplifier usage.
Data Source
AI summary
In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.