Multi-Stage Delta-Sigma Integrator for High-Speed Parallel Modulation
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Solution Overview
Problem
High-speed operation of ΔΣ modulators is limited by the trade-off relationship between the maximum operating frequency and the number of parallel processes, making it difficult to achieve high-speed ΔΣ modulation in wireless communication systems.
Innovation Solution
A ΔΣ modulator using multiple integrators with a configuration of serially connected adder sequences, where the result of a second adder sequence is fed back as input to a first adder sequence, allowing for parallel processing and increasing the operating frequency while maintaining the number of parallel processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the maximum operating frequency M is increased, then the device characteristics improve, but the number of parallel processes N decreases
Solution Approach 1:
The adder sequence is divided into multiple stages (first adder sequence and second adder sequence), with each stage processing a portion of the parallel operations. This segmentation allows the system to maintain high operating frequency while distributing the parallel processing load across multiple stages, thereby resolving the trade-off between speed and productivity.
Solution Approach 2:
The patent introduces a temporal dimension by staging the adder sequences in time (first adder sequence followed by second adder sequence), allowing parallel processes to be completed across multiple time stages rather than requiring all N processes to complete within a single clock cycle. This enables higher operating frequencies while maintaining the total number of parallel processes through multi-stage processing.
2Reliability
If N-fold parallel processing is completed within the time represented by the reciprocal of the maximum operating frequency M, then the calculation is correct, but the time available for processing becomes shorter as M increases
Solution Approach 1:
The first adder sequence performs preliminary parallel processing operations before the second adder sequence completes the remaining calculations. By dividing the parallel processing into preliminary and final stages, the system maintains correctness while distributing the time requirement across multiple clock cycles, thus avoiding the constraint of completing all N parallel operations within a single short time window.
Solution Approach 2:
The patent employs periodic action by executing the first adder sequence in one clock cycle and the second adder sequence in subsequent clock cycles. This periodic multi-cycle execution allows N-fold parallel processing to be completed correctly while extending the total processing time across multiple periods, thereby resolving the conflict between reliability and time loss.
3Productivity
If the operating frequency is increased to achieve high-speed modulation, then the bit rate increases, but the trade-off relationship limits the maximum achievable speed
Solution Approach 1:
By segmenting the adder sequence into multiple stages that can be executed across different clock cycles, the system achieves high bit rates without requiring all N parallel processes to complete at the maximum operating frequency simultaneously. This reduces the effective complexity constraint by distributing the computational load over time.
Solution Approach 2:
The patent maintains continuity of useful action by keeping the adder sequences operating continuously across multiple clock cycles. The first adder sequence processes data in one cycle while the second adder sequence continues processing in subsequent cycles, ensuring that the system maintains high productivity (bit rate) without being limited by the trade-off relationship that would otherwise require reducing N to increase M.
Data Source
AI summary
This ΔΣ modulator is a ΔΣ modulator using multiple integrators. The integrator: includes a plurality of stages of adder sequences, each of the adder sequences including a plurality of adders connected in series; performs feedback of a result of a second adder sequence as an input to a first adder sequence, the first adder sequence being a first stage of the plurality of stages, and the second adder sequence being a last stage of the plurality of stages; and processes inputs supplied to the plurality of adders of the first adder sequence and supplies it to the second adder sequence.