Delta-Sigma Loop Filter Switching for Excess Loop Delay Compensation
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Solution Overview
Problem
Existing delta-sigma modulators face challenges in efficiently compensating for excess loop delay, particularly at high conversion bandwidths and sampling clock rates, which affects stability and resolution, and existing solutions often incur high power consumption.
Innovation Solution
A delta-sigma modulator with a loop filter that employs a time division switching technique to reconfigure its transfer function based on a clock signal, using resistor units with switch-controlled resistance values to compensate for excess loop delay while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a direct feedback path is inserted after the last integrator to compensate for excess loop delay, then excess loop delay compensation is achieved, but power consumption increases due to the wide bandwidth requirement of the summing amplifier
Solution Approach 1:
The patent applies dynamics by making the feedback path configurable - it can be enabled or disabled based on operating conditions. The feedback path includes a switch that allows the system to dynamically activate the compensation mechanism only when needed, rather than continuously operating a high-power wide bandwidth amplifier. This resolves the contradiction by making the power-consuming compensation element dynamic rather than static.
Solution Approach 2:
The patent changes the bandwidth parameter of the summing amplifier by configuring it to operate at different bandwidth levels depending on whether the direct feedback path is active. When the feedback path is disabled, the amplifier can operate at lower bandwidth and thus lower power consumption. This parameter change allows the system to achieve ELD compensation only when necessary, resolving the power consumption issue.
2Productivity
If conversion bandwidth and sampling clock rate are increased to improve performance, then resolution and efficiency are improved, but excess loop delay increases which impairs stability
Solution Approach 1:
The patent introduces a direct feedback path that feeds the quantizer output directly back to the summing node, bypassing the integrators. This creates an additional fast feedback loop that compensates for the excess loop delay introduced by high-speed operation. The feedback mechanism actively counteracts the stability-degrading effects of high conversion bandwidth and sampling clock rate.
Solution Approach 2:
The direct feedback path provides preliminary correction of the loop delay effects by returning the quantizer output directly to the summing node before the signal proceeds through the integrators. This preliminary action compensates for the delay that would otherwise accumulate through the normal signal path, maintaining stability at high operating speeds.
Data Source
AI summary
Proposed is a technology related to a compensation method for excess loop delay (ELD) using a time division switching (TDS) technique. A delta-sigma modulator (DSM) to which the compensation method for excess loop delay is applied includes a single op-amp resonator (SOR) loop filter. The loop filter includes an operational amplifier, a plurality of capacitors connected to each other in series between an input terminal and an output terminal of the operational amplifier, and a plurality of resistor units connected in common to one among nodes between the plurality of capacitors. For at least two of the plurality of resistor units, a resistance value of each of the at least two resistor units is changed according to a clock signal, and a coefficient of a third-order transfer function of the loop filter is changed according to the clock signal, thereby effectively compensating for excess loop delay of the delta-sigma modulator.