Delta-Sigma Modulator Architecture for Low-Latency Isolation
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Solution Overview
Problem
The latency of isolated modulators and amplifiers in control systems is a challenge due to harsh settling requirements, making it difficult to increase clock rates for improved performance.
Innovation Solution
A circuit design incorporating multi-bit analog-to-digital conversion circuitry, interpolation and filter circuitry, and digital delta-sigma modulator, which operates at higher clock rates without increasing the clock frequency, thereby reducing latency and improving bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the clock rate of isolated modulators and amplifiers is increased to reduce latency, then the bandwidth and performance improve, but the settling requirements become harsher and more difficult to meet
Solution Approach 1:
The patent divides the modulator into separate analog and digital domains with distinct clock rates. The analog portion operates at a lower clock rate (e.g., 12.8 MHz) while the digital portion operates at a higher clock rate (e.g., 102.4 MHz), allowing each domain to be optimized independently without compromising settling requirements
Solution Approach 2:
The patent introduces an interpolation stage that operates in the digital domain to upconvert the sampling rate by a factor of L (e.g., 8x). This dimensional transformation from time-domain sampling to frequency-domain interpolation enables high output clock rates without increasing the analog clock rate, thereby maintaining acceptable settling requirements while achieving low latency
2Productivity
If the clock rate is increased to improve bandwidth, then the speed of operation increases, but the settling time requirements become more stringent
Solution Approach 1:
The system separates bandwidth-critical digital processing from settling-critical analog processing. The digital delta-sigma modulator and interpolation circuit operate at high clock rates to achieve wide bandwidth, while the analog-to-digital conversion stage operates at a lower clock rate that satisfies settling time requirements
Solution Approach 2:
The interpolation circuit acts as an intermediary between the low-clock-rate analog domain and the high-clock-rate digital domain. It upconverts the sampling rate without requiring the analog circuits to operate at the higher frequency, thus achieving wide bandwidth while maintaining acceptable settling times
3Speed
If a high clock rate is used to reduce latency, then the response speed improves, but the settling requirements become harsher
Solution Approach 1:
The patent segments the signal processing chain into analog conversion (low speed, high precision) and digital modulation (high speed, lower precision). This allows the analog portion to meet stringent settling precision requirements at lower speeds, while the digital portion can operate at high speeds to achieve low latency
Data Source
AI summary
A circuit includes: multi-bit analog-to-digital conversion circuitry; an interpolation circuit; a filter; and a digital delta-sigma modulator. The multi-bit analog-to-digital conversion circuitry has a first terminal and a second terminal. The interpolation circuit has a first terminal and a second terminal. The first terminal of the interpolation circuit is coupled to the second terminal of the multi-bit analog-to-digital conversion circuitry. The filter has a first terminal and a second terminal. The first terminal of the filter is coupled to the second terminal of the interpolation circuit. The digital delta-sigma modulator has a first terminal and a second terminal. The first terminal of the digital delta-sigma modulator is coupled to the second terminal of the filter.