Delta-Sigma Quantizer Offset Tracking for Low-Voltage SNR

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Solution Overview

Problem

Conventional delta sigma A/D modulators face challenges in reducing circuit area and current consumption while maintaining SNR characteristics when operating at lower power supply voltages, as the determination range of comparators is narrowed, leading to increased determination errors and reduced accuracy.

Innovation Solution

Incorporating a variable gain circuit and an offset addition circuit to control the quantizer's determinable range, allowing the number of comparators to be reduced without increasing accuracy, and using switched capacitor circuits to adjust the offset signal, enabling operation with a smaller number of comparators and maintaining SNR characteristics at lower voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the number of comparators is reduced to lower voltage and reduce power consumption, then power consumption and circuit area are reduced, but the determination range of comparators is narrowed leading to increased determination errors and reduced accuracy

Engineering Contradiction:
Improvepower consumptionVSAvoiddetermination accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent applies dynamics by making the determination range of the quantizer adjustable through a control signal. The determination range is dynamically changed based on the input signal characteristics, allowing the system to adapt the comparator resolution to match the actual signal variation. This enables using fewer comparators while maintaining accuracy by reducing the determination range only when the input signal varies slowly or has small amplitude, thus resolving the contradiction between power consumption and determination accuracy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the determination range parameter of the quantizer dynamically. By adjusting the determination range according to input signal conditions (such as signal amplitude or variation rate), the system can operate with a smaller determination range (fewer comparators) when high precision is not required, thereby reducing power consumption while maintaining sufficient accuracy when needed.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the determination range of the quantizer is reduced to increase comparator accuracy, then determination accuracy is improved, but the number of comparators must be increased leading to increased circuit area and current consumption

Engineering Contradiction:
Improvedetermination accuracyVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent makes the determination range dynamically adjustable rather than fixed. The control signal adjusts the determination range based on actual signal conditions, allowing the system to use a small determination range (and thus fewer comparators) during periods when high precision is not required. This dynamic adaptation eliminates the need to maintain a large fixed determination range at all times, reducing circuit area while maintaining sufficient accuracy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the determination range parameter dynamically based on input signal characteristics. By adjusting this parameter, the system can reduce the number of comparators needed (reducing circuit area) while maintaining determination accuracy when the signal requires it. The parameter change allows flexible trade-off between circuit area and accuracy based on operational conditions.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If the number of comparators is reduced to reduce circuit complexity, then device complexity is reduced, but the quantizer cannot handle a wide input signal range without saturation

Engineering Contradiction:
Improvequantizer complexityVSAvoidinput signal range handling
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the determination range adjustable through a control signal. The system can dynamically expand or contract the determination range based on the input signal characteristics. When the input signal has large amplitude or rapid variation, the determination range is expanded to prevent saturation. When the signal is small or varies slowly, the range is contracted to reduce complexity. This dynamic adjustment resolves the contradiction between device complexity and adaptability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses preliminary action by predicting or detecting the input signal characteristics (such as amplitude or variation rate) and adjusting the determination range in advance. The control signal prepares the quantizer by setting an appropriate determination range before the actual quantization occurs, preventing saturation issues before they arise. This preliminary adjustment allows the system to handle a wide input signal range with fewer comparators.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7855668B2Delta sigma A/D modulator
Publication Date: 2010.12.21 PANASONIC SEMICON SOLUTIONS CO LTD
  • US7855668B2 patent drawing
  • US7855668B2 patent drawing
  • US7855668B2 patent drawing

AI summary

A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.